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@@ -2840,7 +2840,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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enum port port = dp_to_dig_port(intel_dp)->port;
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- if (IS_VALLEYVIEW(dev))
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+ if (INTEL_INFO(dev)->gen >= 9)
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+ return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
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+ else if (IS_VALLEYVIEW(dev))
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return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
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else if (IS_GEN7(dev) && port == PORT_A)
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return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
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@@ -2856,7 +2858,18 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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enum port port = dp_to_dig_port(intel_dp)->port;
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- if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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+ if (INTEL_INFO(dev)->gen >= 9) {
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+ switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
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+ return DP_TRAIN_PRE_EMPH_LEVEL_3;
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+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
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+ return DP_TRAIN_PRE_EMPH_LEVEL_2;
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+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
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+ return DP_TRAIN_PRE_EMPH_LEVEL_1;
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+ default:
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+ return DP_TRAIN_PRE_EMPH_LEVEL_0;
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+ }
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+ } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
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return DP_TRAIN_PRE_EMPH_LEVEL_3;
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@@ -3338,7 +3351,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
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uint32_t signal_levels, mask;
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uint8_t train_set = intel_dp->train_set[0];
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- if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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+ if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
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signal_levels = intel_hsw_signal_levels(train_set);
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mask = DDI_BUF_EMP_MASK;
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} else if (IS_CHERRYVIEW(dev)) {
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