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@@ -0,0 +1,59 @@
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+Binding for the TI specific wrapper for the Cadence USBSS-DRD controller
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+
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+Required properties:
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+ - compatible: Should contain "ti,j721e-usb"
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+ - reg: Physical base address and size of the wrappers register area.
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+ - power-domains: Should contain a phandle to a PM domain provider node
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+ and an args specifier containing the USB device id
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+ value. This property is as per the binding documentation:
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+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
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+ - clocks: Clock phandles to usb2_refclk and lpm_clk
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+ - clock-names: Should contain "usb2_refclk" and "lpm_clk"
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+
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+Optional properties:
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+ - ti,usb2-only: If present, it restricts the controller to USB2.0 mode of
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+ operation. Must be present if USB3 PHY is not available
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+ for USB.
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+ - ti,modestrap-host: Set controller modestrap to HOST mode.
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+ - ti,modestrap-peripheral: Set controller modestrap to PERIPHERAL mode.
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+ - ti,vbus-divider: Should be present if USB VBUS line is connected to the
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+ VBUS pin of the SoC via a 1/3 voltage divider.
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+
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+Sub-nodes:
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+The USB2 PHY and the Cadence USB3 controller should be the sub-nodes.
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+
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+Example:
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+
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+ ti_usb0: cdns_usb@4104000 {
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+ compatible = "ti,j721e-usb";
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+ reg = <0x00 0x4104000 0x00 0x100>;
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+ power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
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+ clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
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+ clock-names = "usb2_refclk", "lpm_clk";
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+ assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
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+ assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ phy@4108000 {
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+ compatible = "ti,j721e-usb2-phy";
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+ reg = <0x00 0x4108000 0x00 0x400>;
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+ };
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+
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+ usb0: usb@6000000 {
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+ compatible = "cdns,usb3-1.0.1";
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+ reg = <0x00 0x6000000 0x00 0x10000>,
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+ <0x00 0x6010000 0x00 0x10000>,
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+ <0x00 0x6020000 0x00 0x10000>;
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+ reg-names = "otg", "xhci", "dev";
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
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+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
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+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
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+ interrupt-names = "host",
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+ "peripheral",
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+ "otg";
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+ maximum-speed = "super-speed";
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+ dr_mode = "otg";
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+ };
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+ };
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