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@@ -19,6 +19,34 @@ enum reg_type {
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REG_TYPE_BASE,
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};
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+/**
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+ * is_string_insn() - Determine if instruction is a string instruction
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+ * @insn: Instruction containing the opcode to inspect
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+ *
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+ * Returns:
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+ *
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+ * true if the instruction, determined by the opcode, is any of the
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+ * string instructions as defined in the Intel Software Development manual.
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+ * False otherwise.
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+ */
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+static bool is_string_insn(struct insn *insn)
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+{
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+ insn_get_opcode(insn);
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+
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+ /* All string instructions have a 1-byte opcode. */
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+ if (insn->opcode.nbytes != 1)
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+ return false;
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+
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+ switch (insn->opcode.bytes[0]) {
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+ case 0x6c ... 0x6f: /* INS, OUTS */
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+ case 0xa4 ... 0xa7: /* MOVS, CMPS */
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+ case 0xaa ... 0xaf: /* STOS, LODS, SCAS */
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+ return true;
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+ default:
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+ return false;
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+ }
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+}
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+
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static int get_reg_offset(struct insn *insn, struct pt_regs *regs,
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enum reg_type type)
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{
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