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@@ -20,6 +20,7 @@
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*/
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#include <asm/irq_regs.h>
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+#include <asm/perf_event.h>
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#include <asm/virt.h>
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#include <linux/of.h>
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@@ -384,9 +385,6 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
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#define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
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(ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
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-#define ARMV8_MAX_COUNTERS 32
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-#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1)
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-
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/*
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* ARMv8 low level PMU access
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*/
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@@ -395,40 +393,7 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
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* Perf Event to low level counters mapping
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*/
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#define ARMV8_IDX_TO_COUNTER(x) \
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- (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
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-
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-/*
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- * Per-CPU PMCR: config reg
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- */
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-#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */
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-#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */
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-#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */
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-#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
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-#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
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-#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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-#define ARMV8_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */
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-#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */
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-#define ARMV8_PMCR_N_MASK 0x1f
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-#define ARMV8_PMCR_MASK 0x7f /* Mask for writable bits */
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-
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-/*
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- * PMOVSR: counters overflow flag status reg
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- */
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-#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */
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-#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK
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-
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-/*
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- * PMXEVTYPER: Event selection reg
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- */
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-#define ARMV8_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */
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-#define ARMV8_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */
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-
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-/*
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- * Event filters for PMUv3
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- */
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-#define ARMV8_EXCLUDE_EL1 (1 << 31)
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-#define ARMV8_EXCLUDE_EL0 (1 << 30)
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-#define ARMV8_INCLUDE_EL2 (1 << 27)
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+ (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
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static inline u32 armv8pmu_pmcr_read(void)
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{
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@@ -439,14 +404,14 @@ static inline u32 armv8pmu_pmcr_read(void)
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static inline void armv8pmu_pmcr_write(u32 val)
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{
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- val &= ARMV8_PMCR_MASK;
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+ val &= ARMV8_PMU_PMCR_MASK;
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isb();
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asm volatile("msr pmcr_el0, %0" :: "r" (val));
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}
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static inline int armv8pmu_has_overflowed(u32 pmovsr)
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{
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- return pmovsr & ARMV8_OVERFLOWED_MASK;
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+ return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
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}
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static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
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@@ -512,7 +477,7 @@ static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
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static inline void armv8pmu_write_evtype(int idx, u32 val)
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{
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if (armv8pmu_select_counter(idx) == idx) {
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- val &= ARMV8_EVTYPE_MASK;
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+ val &= ARMV8_PMU_EVTYPE_MASK;
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asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
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}
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}
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@@ -558,7 +523,7 @@ static inline u32 armv8pmu_getreset_flags(void)
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asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
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/* Write to clear flags */
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- value &= ARMV8_OVSR_MASK;
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+ value &= ARMV8_PMU_OVSR_MASK;
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asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
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return value;
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@@ -696,7 +661,7 @@ static void armv8pmu_start(struct arm_pmu *cpu_pmu)
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raw_spin_lock_irqsave(&events->pmu_lock, flags);
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/* Enable all counters */
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- armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
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+ armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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}
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@@ -707,7 +672,7 @@ static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
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raw_spin_lock_irqsave(&events->pmu_lock, flags);
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/* Disable all counters */
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- armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
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+ armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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}
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@@ -717,7 +682,7 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
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int idx;
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struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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- unsigned long evtype = hwc->config_base & ARMV8_EVTYPE_EVENT;
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+ unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
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/* Always place a cycle counter into the cycle counter. */
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if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
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@@ -754,11 +719,11 @@ static int armv8pmu_set_event_filter(struct hw_perf_event *event,
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attr->exclude_kernel != attr->exclude_hv)
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return -EINVAL;
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if (attr->exclude_user)
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- config_base |= ARMV8_EXCLUDE_EL0;
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+ config_base |= ARMV8_PMU_EXCLUDE_EL0;
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if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
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- config_base |= ARMV8_EXCLUDE_EL1;
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+ config_base |= ARMV8_PMU_EXCLUDE_EL1;
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if (!attr->exclude_hv)
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- config_base |= ARMV8_INCLUDE_EL2;
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+ config_base |= ARMV8_PMU_INCLUDE_EL2;
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/*
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* Install the filter into config_base as this is used to
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@@ -784,35 +749,36 @@ static void armv8pmu_reset(void *info)
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* Initialize & Reset PMNC. Request overflow interrupt for
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* 64 bit cycle counter but cheat in armv8pmu_write_counter().
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*/
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- armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C | ARMV8_PMCR_LC);
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+ armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
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+ ARMV8_PMU_PMCR_LC);
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}
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static int armv8_pmuv3_map_event(struct perf_event *event)
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{
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return armpmu_map_event(event, &armv8_pmuv3_perf_map,
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&armv8_pmuv3_perf_cache_map,
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- ARMV8_EVTYPE_EVENT);
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+ ARMV8_PMU_EVTYPE_EVENT);
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}
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static int armv8_a53_map_event(struct perf_event *event)
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{
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return armpmu_map_event(event, &armv8_a53_perf_map,
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&armv8_a53_perf_cache_map,
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- ARMV8_EVTYPE_EVENT);
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+ ARMV8_PMU_EVTYPE_EVENT);
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}
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static int armv8_a57_map_event(struct perf_event *event)
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{
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return armpmu_map_event(event, &armv8_a57_perf_map,
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&armv8_a57_perf_cache_map,
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- ARMV8_EVTYPE_EVENT);
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+ ARMV8_PMU_EVTYPE_EVENT);
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}
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static int armv8_thunder_map_event(struct perf_event *event)
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{
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return armpmu_map_event(event, &armv8_thunder_perf_map,
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&armv8_thunder_perf_cache_map,
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- ARMV8_EVTYPE_EVENT);
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+ ARMV8_PMU_EVTYPE_EVENT);
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}
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static void armv8pmu_read_num_pmnc_events(void *info)
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@@ -820,7 +786,7 @@ static void armv8pmu_read_num_pmnc_events(void *info)
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int *nb_cnt = info;
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/* Read the nb of CNTx counters supported from PMNC */
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- *nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
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+ *nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
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/* Add the CPU cycles counter */
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*nb_cnt += 1;
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Linus Torvalds