|
|
@@ -163,7 +163,7 @@ static void iwl_pcie_txq_stuck_timer(unsigned long data)
|
|
|
spin_unlock(&txq->lock);
|
|
|
|
|
|
IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
|
|
|
- jiffies_to_msecs(trans_pcie->wd_timeout));
|
|
|
+ jiffies_to_msecs(txq->wd_timeout));
|
|
|
IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
|
|
|
txq->q.read_ptr, txq->q.write_ptr);
|
|
|
|
|
|
@@ -674,7 +674,8 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
|
|
|
iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
|
|
|
|
|
|
iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
|
|
|
- trans_pcie->cmd_fifo);
|
|
|
+ trans_pcie->cmd_fifo,
|
|
|
+ trans_pcie->cmd_q_wdg_timeout);
|
|
|
|
|
|
/* Activate all Tx DMA/FIFO channels */
|
|
|
iwl_scd_activate_fifos(trans);
|
|
|
@@ -909,10 +910,9 @@ error:
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
|
|
|
- struct iwl_txq *txq)
|
|
|
+static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
|
|
|
{
|
|
|
- if (!trans_pcie->wd_timeout)
|
|
|
+ if (!txq->wd_timeout)
|
|
|
return;
|
|
|
|
|
|
/*
|
|
|
@@ -922,7 +922,7 @@ static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
|
|
|
if (txq->q.read_ptr == txq->q.write_ptr)
|
|
|
del_timer(&txq->stuck_timer);
|
|
|
else
|
|
|
- mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
|
|
|
+ mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
|
|
|
}
|
|
|
|
|
|
/* Frees buffers until index _not_ inclusive */
|
|
|
@@ -984,7 +984,7 @@ void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
|
|
|
iwl_pcie_txq_free_tfd(trans, txq);
|
|
|
}
|
|
|
|
|
|
- iwl_pcie_txq_progress(trans_pcie, txq);
|
|
|
+ iwl_pcie_txq_progress(txq);
|
|
|
|
|
|
if (iwl_queue_space(&txq->q) > txq->q.low_mark)
|
|
|
iwl_wake_queue(trans, txq);
|
|
|
@@ -1112,7 +1112,7 @@ static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
|
|
|
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
|
|
}
|
|
|
|
|
|
- iwl_pcie_txq_progress(trans_pcie, txq);
|
|
|
+ iwl_pcie_txq_progress(txq);
|
|
|
}
|
|
|
|
|
|
static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
|
|
|
@@ -1145,14 +1145,18 @@ static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
|
|
|
#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
|
|
|
|
|
|
void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
|
|
|
- const struct iwl_trans_txq_scd_cfg *cfg)
|
|
|
+ const struct iwl_trans_txq_scd_cfg *cfg,
|
|
|
+ unsigned int wdg_timeout)
|
|
|
{
|
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+ struct iwl_txq *txq = &trans_pcie->txq[txq_id];
|
|
|
int fifo = -1;
|
|
|
|
|
|
if (test_and_set_bit(txq_id, trans_pcie->queue_used))
|
|
|
WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
|
|
|
|
|
|
+ txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
|
|
|
+
|
|
|
if (cfg) {
|
|
|
fifo = cfg->fifo;
|
|
|
|
|
|
@@ -1176,7 +1180,7 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
|
|
|
|
|
|
/* enable aggregations for the queue */
|
|
|
iwl_scd_txq_enable_agg(trans, txq_id);
|
|
|
- trans_pcie->txq[txq_id].ampdu = true;
|
|
|
+ txq->ampdu = true;
|
|
|
} else {
|
|
|
/*
|
|
|
* disable aggregations for the queue, this will also
|
|
|
@@ -1185,14 +1189,14 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
|
|
|
*/
|
|
|
iwl_scd_txq_disable_agg(trans, txq_id);
|
|
|
|
|
|
- ssn = trans_pcie->txq[txq_id].q.read_ptr;
|
|
|
+ ssn = txq->q.read_ptr;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Place first TFD at index corresponding to start sequence number.
|
|
|
* Assumes that ssn_idx is valid (!= 0xFFF) */
|
|
|
- trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
|
|
|
- trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
|
|
|
+ txq->q.read_ptr = (ssn & 0xff);
|
|
|
+ txq->q.write_ptr = (ssn & 0xff);
|
|
|
iwl_write_direct32(trans, HBUS_TARG_WRPTR,
|
|
|
(ssn & 0xff) | (txq_id << 8));
|
|
|
|
|
|
@@ -1233,7 +1237,7 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
|
|
|
txq_id, ssn & 0xff);
|
|
|
}
|
|
|
|
|
|
- trans_pcie->txq[txq_id].active = true;
|
|
|
+ txq->active = true;
|
|
|
}
|
|
|
|
|
|
void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
|
|
|
@@ -1498,8 +1502,8 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
|
|
|
trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
|
|
|
|
|
|
/* start timer if queue currently empty */
|
|
|
- if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
|
|
|
- mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
|
|
|
+ if (q->read_ptr == q->write_ptr && txq->wd_timeout)
|
|
|
+ mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
|
|
|
|
|
|
spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
|
|
ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
|
|
|
@@ -1849,9 +1853,8 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
|
|
|
|
|
/* start timer if queue currently empty */
|
|
|
if (q->read_ptr == q->write_ptr) {
|
|
|
- if (trans_pcie->wd_timeout)
|
|
|
- mod_timer(&txq->stuck_timer,
|
|
|
- jiffies + trans_pcie->wd_timeout);
|
|
|
+ if (txq->wd_timeout)
|
|
|
+ mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
|
|
|
IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
|
|
|
iwl_trans_pcie_ref(trans);
|
|
|
}
|