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@@ -481,8 +481,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
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| AR_Q_MISC_CBR_INCR_DIS0);
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value = (qi->tqi_readyTime -
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(ah->config.sw_beacon_response_time -
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- ah->config.dma_beacon_response_time) -
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- ah->config.additional_swba_backoff) * 1024;
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+ ah->config.dma_beacon_response_time)) * 1024;
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REG_WRITE(ah, AR_QRDYTIMECFG(q),
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value | AR_Q_RDYTIMECFG_EN);
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REG_SET_BIT(ah, AR_DMISC(q),
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