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@@ -245,82 +245,6 @@ static unsigned int mite_fifo_size(struct mite *mite, unsigned int channel)
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return empty_count + full_count;
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return empty_count + full_count;
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}
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}
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-int mite_setup2(struct comedi_device *dev,
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- struct mite *mite, bool use_win1)
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-{
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- resource_size_t daq_phys_addr;
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- unsigned long length;
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- int i;
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- u32 csigr_bits;
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- unsigned int unknown_dma_burst_bits;
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-
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- pci_set_master(mite->pcidev);
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-
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- mite->mmio = pci_ioremap_bar(mite->pcidev, 0);
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- if (!mite->mmio) {
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- dev_err(dev->class_dev,
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- "Failed to remap mite io memory address\n");
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- return -ENOMEM;
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- }
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-
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- dev->mmio = pci_ioremap_bar(mite->pcidev, 1);
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- if (!dev->mmio) {
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- dev_err(dev->class_dev,
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- "Failed to remap daq io memory address\n");
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- return -ENOMEM;
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- }
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- daq_phys_addr = pci_resource_start(mite->pcidev, 1);
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- length = pci_resource_len(mite->pcidev, 1);
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-
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- if (use_win1) {
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- writel(0, mite->mmio + MITE_IODWBSR);
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- dev_info(dev->class_dev,
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- "using I/O Window Base Size register 1\n");
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- writel(daq_phys_addr | WENAB |
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- MITE_IODWBSR_1_WSIZE_bits(length),
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- mite->mmio + MITE_IODWBSR_1);
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- writel(0, mite->mmio + MITE_IODWCR_1);
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- } else {
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- writel(daq_phys_addr | WENAB, mite->mmio + MITE_IODWBSR);
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- }
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- /*
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- * Make sure dma bursts work. I got this from running a bus analyzer
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- * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
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- * of 0x61f and bursts worked. 6281 powered up with register value of
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- * 0x1f and bursts didn't work. The NI windows driver reads the
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- * register, then does a bitwise-or of 0x600 with it and writes it back.
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- *
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- * The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
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- * written and read back. The bits 0x1f always read as 1.
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- * The rest always read as zero.
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- */
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- unknown_dma_burst_bits = readl(mite->mmio + MITE_UNKNOWN_DMA_BURST_REG);
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- unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
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- writel(unknown_dma_burst_bits, mite->mmio + MITE_UNKNOWN_DMA_BURST_REG);
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-
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- csigr_bits = readl(mite->mmio + MITE_CSIGR);
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- mite->num_channels = CSIGR_TO_DMAC(csigr_bits);
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- if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
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- dev_warn(dev->class_dev,
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- "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
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- mite->num_channels, MAX_MITE_DMA_CHANNELS);
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- mite->num_channels = MAX_MITE_DMA_CHANNELS;
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- }
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- dump_chip_signature(csigr_bits);
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- for (i = 0; i < mite->num_channels; i++) {
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- writel(CHOR_DMARESET, mite->mmio + MITE_CHOR(i));
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- /* disable interrupts */
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- writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
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- CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
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- CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
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- mite->mmio + MITE_CHCR(i));
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- }
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- mite->fifo_size = mite_fifo_size(mite, 0);
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- dev_info(dev->class_dev, "fifo size is %i.\n", mite->fifo_size);
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- return 0;
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-}
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-EXPORT_SYMBOL_GPL(mite_setup2);
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-
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struct mite_ring *mite_alloc_ring(struct mite *mite)
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struct mite_ring *mite_alloc_ring(struct mite *mite)
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{
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{
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struct mite_ring *ring;
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struct mite_ring *ring;
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@@ -807,31 +731,118 @@ int mite_done(struct mite_channel *mite_chan)
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}
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}
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EXPORT_SYMBOL_GPL(mite_done);
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EXPORT_SYMBOL_GPL(mite_done);
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+static int mite_setup(struct comedi_device *dev, struct mite *mite,
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+ bool use_win1)
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+{
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+ resource_size_t daq_phys_addr;
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+ unsigned long length;
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+ int i;
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+ u32 csigr_bits;
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+ unsigned int unknown_dma_burst_bits;
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+
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+ pci_set_master(mite->pcidev);
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+
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+ mite->mmio = pci_ioremap_bar(mite->pcidev, 0);
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+ if (!mite->mmio) {
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+ dev_err(dev->class_dev,
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+ "Failed to remap mite io memory address\n");
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+ return -ENOMEM;
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+ }
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+
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+ dev->mmio = pci_ioremap_bar(mite->pcidev, 1);
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+ if (!dev->mmio) {
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+ dev_err(dev->class_dev,
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+ "Failed to remap daq io memory address\n");
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+ return -ENOMEM;
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+ }
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+ daq_phys_addr = pci_resource_start(mite->pcidev, 1);
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+ length = pci_resource_len(mite->pcidev, 1);
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+
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+ if (use_win1) {
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+ writel(0, mite->mmio + MITE_IODWBSR);
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+ dev_info(dev->class_dev,
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+ "using I/O Window Base Size register 1\n");
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+ writel(daq_phys_addr | WENAB |
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+ MITE_IODWBSR_1_WSIZE_bits(length),
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+ mite->mmio + MITE_IODWBSR_1);
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+ writel(0, mite->mmio + MITE_IODWCR_1);
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+ } else {
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+ writel(daq_phys_addr | WENAB, mite->mmio + MITE_IODWBSR);
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+ }
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+ /*
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+ * Make sure dma bursts work. I got this from running a bus analyzer
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+ * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
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+ * of 0x61f and bursts worked. 6281 powered up with register value of
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+ * 0x1f and bursts didn't work. The NI windows driver reads the
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+ * register, then does a bitwise-or of 0x600 with it and writes it back.
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+ *
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+ * The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
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+ * written and read back. The bits 0x1f always read as 1.
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+ * The rest always read as zero.
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+ */
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+ unknown_dma_burst_bits = readl(mite->mmio + MITE_UNKNOWN_DMA_BURST_REG);
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+ unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
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+ writel(unknown_dma_burst_bits, mite->mmio + MITE_UNKNOWN_DMA_BURST_REG);
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+
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+ csigr_bits = readl(mite->mmio + MITE_CSIGR);
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+ mite->num_channels = CSIGR_TO_DMAC(csigr_bits);
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+ if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
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+ dev_warn(dev->class_dev,
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+ "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
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+ mite->num_channels, MAX_MITE_DMA_CHANNELS);
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+ mite->num_channels = MAX_MITE_DMA_CHANNELS;
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+ }
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+ dump_chip_signature(csigr_bits);
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+ for (i = 0; i < mite->num_channels; i++) {
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+ writel(CHOR_DMARESET, mite->mmio + MITE_CHOR(i));
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+ /* disable interrupts */
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+ writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
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+ CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
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+ CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
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+ mite->mmio + MITE_CHCR(i));
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+ }
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+ mite->fifo_size = mite_fifo_size(mite, 0);
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+ dev_info(dev->class_dev, "fifo size is %i.\n", mite->fifo_size);
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+ return 0;
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+}
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+
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/**
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/**
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* mite_attach() - Allocate and initialize a MITE device for a comedi driver.
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* mite_attach() - Allocate and initialize a MITE device for a comedi driver.
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* @dev: COMEDI device.
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* @dev: COMEDI device.
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+ * @use_win1: flag to use I/O Window 1 instead of I/O Window 0.
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*
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*
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* Called by a COMEDI drivers (*auto_attach).
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* Called by a COMEDI drivers (*auto_attach).
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*
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*
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* Returns a pointer to the MITE device on success, or NULL if the MITE cannot
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* Returns a pointer to the MITE device on success, or NULL if the MITE cannot
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- * be allocated.
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+ * be allocated or remapped.
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*/
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*/
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-struct mite *mite_attach(struct comedi_device *dev)
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+struct mite *mite_attach(struct comedi_device *dev, bool use_win1)
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{
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{
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struct pci_dev *pcidev = comedi_to_pci_dev(dev);
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struct pci_dev *pcidev = comedi_to_pci_dev(dev);
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struct mite *mite;
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struct mite *mite;
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unsigned int i;
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unsigned int i;
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+ int ret;
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mite = kzalloc(sizeof(*mite), GFP_KERNEL);
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mite = kzalloc(sizeof(*mite), GFP_KERNEL);
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- if (mite) {
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- spin_lock_init(&mite->lock);
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- mite->pcidev = pcidev;
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- for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
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- mite->channels[i].mite = mite;
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- mite->channels[i].channel = i;
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- mite->channels[i].done = 1;
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- }
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+ if (!mite)
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+ return NULL;
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+
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+ spin_lock_init(&mite->lock);
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+ mite->pcidev = pcidev;
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+ for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
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+ mite->channels[i].mite = mite;
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+ mite->channels[i].channel = i;
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+ mite->channels[i].done = 1;
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}
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}
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+
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+ ret = mite_setup(dev, mite, use_win1);
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+ if (ret) {
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+ if (mite->mmio)
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+ iounmap(mite->mmio);
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+ kfree(mite);
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+ return NULL;
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+ }
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+
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return mite;
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return mite;
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}
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}
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EXPORT_SYMBOL_GPL(mite_attach);
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EXPORT_SYMBOL_GPL(mite_attach);
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