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@@ -23,7 +23,7 @@
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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-
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+#include <linux/iopoll.h>
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#include <linux/can/dev.h>
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/* napi related */
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@@ -37,17 +37,19 @@ enum m_can_reg {
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M_CAN_CREL = 0x0,
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M_CAN_ENDN = 0x4,
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M_CAN_CUST = 0x8,
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- M_CAN_FBTP = 0xc,
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+ M_CAN_DBTP = 0xc,
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M_CAN_TEST = 0x10,
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M_CAN_RWD = 0x14,
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M_CAN_CCCR = 0x18,
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- M_CAN_BTP = 0x1c,
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+ M_CAN_NBTP = 0x1c,
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M_CAN_TSCC = 0x20,
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M_CAN_TSCV = 0x24,
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M_CAN_TOCC = 0x28,
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M_CAN_TOCV = 0x2c,
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M_CAN_ECR = 0x40,
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M_CAN_PSR = 0x44,
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+/* TDCR Register only available for version >=3.1.x */
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+ M_CAN_TDCR = 0x48,
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M_CAN_IR = 0x50,
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M_CAN_IE = 0x54,
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M_CAN_ILS = 0x58,
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@@ -105,21 +107,29 @@ enum m_can_mram_cfg {
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MRAM_CFG_NUM,
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};
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-/* Fast Bit Timing & Prescaler Register (FBTP) */
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-#define FBTR_FBRP_MASK 0x1f
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-#define FBTR_FBRP_SHIFT 16
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-#define FBTR_FTSEG1_SHIFT 8
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-#define FBTR_FTSEG1_MASK (0xf << FBTR_FTSEG1_SHIFT)
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-#define FBTR_FTSEG2_SHIFT 4
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-#define FBTR_FTSEG2_MASK (0x7 << FBTR_FTSEG2_SHIFT)
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-#define FBTR_FSJW_SHIFT 0
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-#define FBTR_FSJW_MASK 0x3
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+/* Core Release Register (CREL) */
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+#define CREL_REL_SHIFT 28
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+#define CREL_REL_MASK (0xF << CREL_REL_SHIFT)
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+#define CREL_STEP_SHIFT 24
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+#define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT)
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+#define CREL_SUBSTEP_SHIFT 20
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+#define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT)
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+
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+/* Data Bit Timing & Prescaler Register (DBTP) */
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+#define DBTP_TDC BIT(23)
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+#define DBTP_DBRP_SHIFT 16
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+#define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT)
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+#define DBTP_DTSEG1_SHIFT 8
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+#define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
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+#define DBTP_DTSEG2_SHIFT 4
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+#define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
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+#define DBTP_DSJW_SHIFT 0
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+#define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
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/* Test Register (TEST) */
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-#define TEST_LBCK BIT(4)
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+#define TEST_LBCK BIT(4)
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/* CC Control Register(CCCR) */
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-#define CCCR_TEST BIT(7)
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#define CCCR_CMR_MASK 0x3
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#define CCCR_CMR_SHIFT 10
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#define CCCR_CMR_CANFD 0x1
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@@ -130,21 +140,32 @@ enum m_can_mram_cfg {
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#define CCCR_CME_CAN 0
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#define CCCR_CME_CANFD 0x1
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#define CCCR_CME_CANFD_BRS 0x2
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+#define CCCR_TXP BIT(14)
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#define CCCR_TEST BIT(7)
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#define CCCR_MON BIT(5)
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+#define CCCR_CSR BIT(4)
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+#define CCCR_CSA BIT(3)
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+#define CCCR_ASM BIT(2)
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#define CCCR_CCE BIT(1)
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#define CCCR_INIT BIT(0)
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#define CCCR_CANFD 0x10
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-
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-/* Bit Timing & Prescaler Register (BTP) */
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-#define BTR_BRP_MASK 0x3ff
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-#define BTR_BRP_SHIFT 16
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-#define BTR_TSEG1_SHIFT 8
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-#define BTR_TSEG1_MASK (0x3f << BTR_TSEG1_SHIFT)
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-#define BTR_TSEG2_SHIFT 4
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-#define BTR_TSEG2_MASK (0xf << BTR_TSEG2_SHIFT)
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-#define BTR_SJW_SHIFT 0
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-#define BTR_SJW_MASK 0xf
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+/* for version >=3.1.x */
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+#define CCCR_EFBI BIT(13)
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+#define CCCR_PXHD BIT(12)
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+#define CCCR_BRSE BIT(9)
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+#define CCCR_FDOE BIT(8)
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+/* only for version >=3.2.x */
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+#define CCCR_NISO BIT(15)
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+
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+/* Nominal Bit Timing & Prescaler Register (NBTP) */
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+#define NBTP_NSJW_SHIFT 25
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+#define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
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+#define NBTP_NBRP_SHIFT 16
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+#define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT)
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+#define NBTP_NTSEG1_SHIFT 8
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+#define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT)
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+#define NBTP_NTSEG2_SHIFT 0
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+#define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
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/* Error Counter Register(ECR) */
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#define ECR_RP BIT(15)
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@@ -161,6 +182,13 @@ enum m_can_mram_cfg {
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/* Interrupt Register(IR) */
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#define IR_ALL_INT 0xffffffff
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+
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+/* Renamed bits for versions > 3.1.x */
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+#define IR_ARA BIT(29)
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+#define IR_PED BIT(28)
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+#define IR_PEA BIT(27)
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+
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+/* Bits for version 3.0.x */
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#define IR_STE BIT(31)
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#define IR_FOE BIT(30)
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#define IR_ACKE BIT(29)
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@@ -194,33 +222,40 @@ enum m_can_mram_cfg {
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#define IR_RF0W BIT(1)
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#define IR_RF0N BIT(0)
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#define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
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-#define IR_ERR_LEC (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
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-#define IR_ERR_BUS (IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \
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+
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+/* Interrupts for version 3.0.x */
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+#define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
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+#define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \
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IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
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IR_RF1L | IR_RF0L)
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-#define IR_ERR_ALL (IR_ERR_STATE | IR_ERR_BUS)
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+#define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
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+/* Interrupts for version >= 3.1.x */
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+#define IR_ERR_LEC_31X (IR_PED | IR_PEA)
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+#define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
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+ IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
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+ IR_RF1L | IR_RF0L)
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+#define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
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/* Interrupt Line Select (ILS) */
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#define ILS_ALL_INT0 0x0
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#define ILS_ALL_INT1 0xFFFFFFFF
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/* Interrupt Line Enable (ILE) */
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-#define ILE_EINT0 BIT(0)
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#define ILE_EINT1 BIT(1)
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+#define ILE_EINT0 BIT(0)
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/* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
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-#define RXFC_FWM_OFF 24
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-#define RXFC_FWM_MASK 0x7f
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-#define RXFC_FWM_1 (1 << RXFC_FWM_OFF)
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-#define RXFC_FS_OFF 16
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-#define RXFC_FS_MASK 0x7f
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+#define RXFC_FWM_SHIFT 24
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+#define RXFC_FWM_MASK (0x7f < RXFC_FWM_SHIFT)
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+#define RXFC_FS_SHIFT 16
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+#define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT)
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/* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
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#define RXFS_RFL BIT(25)
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#define RXFS_FF BIT(24)
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-#define RXFS_FPI_OFF 16
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+#define RXFS_FPI_SHIFT 16
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#define RXFS_FPI_MASK 0x3f0000
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-#define RXFS_FGI_OFF 8
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+#define RXFS_FGI_SHIFT 8
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#define RXFS_FGI_MASK 0x3f00
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#define RXFS_FFL_MASK 0x7f
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@@ -229,23 +264,46 @@ enum m_can_mram_cfg {
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#define M_CAN_RXESC_64BYTES 0x777
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/* Tx Buffer Configuration(TXBC) */
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-#define TXBC_NDTB_OFF 16
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-#define TXBC_NDTB_MASK 0x3f
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+#define TXBC_NDTB_SHIFT 16
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+#define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT)
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+#define TXBC_TFQS_SHIFT 24
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+#define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT)
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+
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+/* Tx FIFO/Queue Status (TXFQS) */
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+#define TXFQS_TFQF BIT(21)
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+#define TXFQS_TFQPI_SHIFT 16
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+#define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT)
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+#define TXFQS_TFGI_SHIFT 8
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+#define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT)
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+#define TXFQS_TFFL_SHIFT 0
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+#define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT)
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/* Tx Buffer Element Size Configuration(TXESC) */
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#define TXESC_TBDS_8BYTES 0x0
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#define TXESC_TBDS_64BYTES 0x7
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-/* Tx Event FIFO Con.guration (TXEFC) */
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-#define TXEFC_EFS_OFF 16
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-#define TXEFC_EFS_MASK 0x3f
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+/* Tx Event FIFO Configuration (TXEFC) */
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+#define TXEFC_EFS_SHIFT 16
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+#define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT)
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+
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+/* Tx Event FIFO Status (TXEFS) */
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+#define TXEFS_TEFL BIT(25)
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+#define TXEFS_EFF BIT(24)
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+#define TXEFS_EFGI_SHIFT 8
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+#define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT)
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+#define TXEFS_EFFL_SHIFT 0
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+#define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT)
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+
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+/* Tx Event FIFO Acknowledge (TXEFA) */
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+#define TXEFA_EFAI_SHIFT 0
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+#define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT)
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/* Message RAM Configuration (in bytes) */
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#define SIDF_ELEMENT_SIZE 4
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#define XIDF_ELEMENT_SIZE 8
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#define RXF0_ELEMENT_SIZE 72
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#define RXF1_ELEMENT_SIZE 72
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-#define RXB_ELEMENT_SIZE 16
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+#define RXB_ELEMENT_SIZE 72
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#define TXE_ELEMENT_SIZE 8
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#define TXB_ELEMENT_SIZE 72
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@@ -261,13 +319,25 @@ enum m_can_mram_cfg {
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#define RX_BUF_RTR BIT(29)
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/* R1 */
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#define RX_BUF_ANMF BIT(31)
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-#define RX_BUF_EDL BIT(21)
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+#define RX_BUF_FDF BIT(21)
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#define RX_BUF_BRS BIT(20)
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/* Tx Buffer Element */
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-/* R0 */
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+/* T0 */
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+#define TX_BUF_ESI BIT(31)
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#define TX_BUF_XTD BIT(30)
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#define TX_BUF_RTR BIT(29)
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+/* T1 */
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+#define TX_BUF_EFC BIT(23)
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+#define TX_BUF_FDF BIT(21)
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+#define TX_BUF_BRS BIT(20)
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+#define TX_BUF_MM_SHIFT 24
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+#define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
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+
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+/* Tx event FIFO Element */
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+/* E1 */
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+#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
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+#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
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/* address offset and element number for each FIFO/Buffer in the Message RAM */
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struct mram_cfg {
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@@ -285,6 +355,7 @@ struct m_can_priv {
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struct clk *cclk;
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void __iomem *base;
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u32 irqstatus;
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+ int version;
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/* message ram configuration */
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void __iomem *mram_base;
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@@ -316,6 +387,18 @@ static inline void m_can_fifo_write(const struct m_can_priv *priv,
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fpi * TXB_ELEMENT_SIZE + offset);
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}
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+static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv,
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+ u32 fgi,
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+ u32 offset) {
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+ return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off +
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+ fgi * TXE_ELEMENT_SIZE + offset);
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+}
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+
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+static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv)
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+{
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+ return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF);
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+}
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+
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static inline void m_can_config_endisable(const struct m_can_priv *priv,
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bool enable)
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{
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@@ -349,7 +432,8 @@ static inline void m_can_config_endisable(const struct m_can_priv *priv,
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static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
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{
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- m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1);
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+ /* Only interrupt line 0 is used in this driver */
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+ m_can_write(priv, M_CAN_ILE, ILE_EINT0);
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}
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static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
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@@ -367,9 +451,9 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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int i;
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/* calculate the fifo get index for where to read data */
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- fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
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+ fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
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dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
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- if (dlc & RX_BUF_EDL)
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+ if (dlc & RX_BUF_FDF)
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skb = alloc_canfd_skb(dev, &cf);
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else
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skb = alloc_can_skb(dev, (struct can_frame **)&cf);
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@@ -378,7 +462,7 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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return;
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}
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- if (dlc & RX_BUF_EDL)
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+ if (dlc & RX_BUF_FDF)
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cf->len = can_dlc2len((dlc >> 16) & 0x0F);
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else
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cf->len = get_can_dlc((dlc >> 16) & 0x0F);
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@@ -394,7 +478,7 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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netdev_dbg(dev, "ESI Error\n");
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}
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- if (!(dlc & RX_BUF_EDL) && (id & RX_BUF_RTR)) {
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+ if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) {
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cf->can_id |= CAN_RTR_FLAG;
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} else {
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if (dlc & RX_BUF_BRS)
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@@ -532,7 +616,7 @@ static int __m_can_get_berr_counter(const struct net_device *dev,
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ecr = m_can_read(priv, M_CAN_ECR);
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bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
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- bec->txerr = ecr & ECR_TEC_MASK;
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+ bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
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return 0;
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}
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@@ -723,7 +807,7 @@ static int m_can_poll(struct napi_struct *napi, int quota)
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if (irqstatus & IR_ERR_STATE)
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work_done += m_can_handle_state_errors(dev, psr);
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- if (irqstatus & IR_ERR_BUS)
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+ if (irqstatus & IR_ERR_BUS_30X)
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work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
|
|
|
|
|
|
if (irqstatus & IR_RF0N)
|
|
|
@@ -738,6 +822,44 @@ end:
|
|
|
return work_done;
|
|
|
}
|
|
|
|
|
|
+static void m_can_echo_tx_event(struct net_device *dev)
|
|
|
+{
|
|
|
+ u32 txe_count = 0;
|
|
|
+ u32 m_can_txefs;
|
|
|
+ u32 fgi = 0;
|
|
|
+ int i = 0;
|
|
|
+ unsigned int msg_mark;
|
|
|
+
|
|
|
+ struct m_can_priv *priv = netdev_priv(dev);
|
|
|
+ struct net_device_stats *stats = &dev->stats;
|
|
|
+
|
|
|
+ /* read tx event fifo status */
|
|
|
+ m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
|
|
|
+
|
|
|
+ /* Get Tx Event fifo element count */
|
|
|
+ txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
|
|
|
+ >> TXEFS_EFFL_SHIFT;
|
|
|
+
|
|
|
+ /* Get and process all sent elements */
|
|
|
+ for (i = 0; i < txe_count; i++) {
|
|
|
+ /* retrieve get index */
|
|
|
+ fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
|
|
|
+ >> TXEFS_EFGI_SHIFT;
|
|
|
+
|
|
|
+ /* get message marker */
|
|
|
+ msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
|
|
|
+ TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
|
|
|
+
|
|
|
+ /* ack txe element */
|
|
|
+ m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
|
|
|
+ (fgi << TXEFA_EFAI_SHIFT)));
|
|
|
+
|
|
|
+ /* update stats */
|
|
|
+ stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
|
|
|
+ stats->tx_packets++;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
static irqreturn_t m_can_isr(int irq, void *dev_id)
|
|
|
{
|
|
|
struct net_device *dev = (struct net_device *)dev_id;
|
|
|
@@ -758,24 +880,35 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
|
|
|
* - state change IRQ
|
|
|
* - bus error IRQ and bus error reporting
|
|
|
*/
|
|
|
- if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) {
|
|
|
+ if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
|
|
|
priv->irqstatus = ir;
|
|
|
m_can_disable_all_interrupts(priv);
|
|
|
napi_schedule(&priv->napi);
|
|
|
}
|
|
|
|
|
|
- /* transmission complete interrupt */
|
|
|
- if (ir & IR_TC) {
|
|
|
- stats->tx_bytes += can_get_echo_skb(dev, 0);
|
|
|
- stats->tx_packets++;
|
|
|
- can_led_event(dev, CAN_LED_EVENT_TX);
|
|
|
- netif_wake_queue(dev);
|
|
|
+ if (priv->version == 30) {
|
|
|
+ if (ir & IR_TC) {
|
|
|
+ /* Transmission Complete Interrupt*/
|
|
|
+ stats->tx_bytes += can_get_echo_skb(dev, 0);
|
|
|
+ stats->tx_packets++;
|
|
|
+ can_led_event(dev, CAN_LED_EVENT_TX);
|
|
|
+ netif_wake_queue(dev);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ if (ir & IR_TEFN) {
|
|
|
+ /* New TX FIFO Element arrived */
|
|
|
+ m_can_echo_tx_event(dev);
|
|
|
+ can_led_event(dev, CAN_LED_EVENT_TX);
|
|
|
+ if (netif_queue_stopped(dev) &&
|
|
|
+ !m_can_tx_fifo_full(priv))
|
|
|
+ netif_wake_queue(dev);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
}
|
|
|
|
|
|
-static const struct can_bittiming_const m_can_bittiming_const = {
|
|
|
+static const struct can_bittiming_const m_can_bittiming_const_30X = {
|
|
|
.name = KBUILD_MODNAME,
|
|
|
.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
|
|
|
.tseg1_max = 64,
|
|
|
@@ -787,7 +920,7 @@ static const struct can_bittiming_const m_can_bittiming_const = {
|
|
|
.brp_inc = 1,
|
|
|
};
|
|
|
|
|
|
-static const struct can_bittiming_const m_can_data_bittiming_const = {
|
|
|
+static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
|
|
|
.name = KBUILD_MODNAME,
|
|
|
.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
|
|
|
.tseg1_max = 16,
|
|
|
@@ -799,6 +932,30 @@ static const struct can_bittiming_const m_can_data_bittiming_const = {
|
|
|
.brp_inc = 1,
|
|
|
};
|
|
|
|
|
|
+static const struct can_bittiming_const m_can_bittiming_const_31X = {
|
|
|
+ .name = KBUILD_MODNAME,
|
|
|
+ .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
|
|
|
+ .tseg1_max = 256,
|
|
|
+ .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
|
|
|
+ .tseg2_max = 128,
|
|
|
+ .sjw_max = 128,
|
|
|
+ .brp_min = 1,
|
|
|
+ .brp_max = 512,
|
|
|
+ .brp_inc = 1,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
|
|
|
+ .name = KBUILD_MODNAME,
|
|
|
+ .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
|
|
|
+ .tseg1_max = 32,
|
|
|
+ .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
|
|
|
+ .tseg2_max = 16,
|
|
|
+ .sjw_max = 16,
|
|
|
+ .brp_min = 1,
|
|
|
+ .brp_max = 32,
|
|
|
+ .brp_inc = 1,
|
|
|
+};
|
|
|
+
|
|
|
static int m_can_set_bittiming(struct net_device *dev)
|
|
|
{
|
|
|
struct m_can_priv *priv = netdev_priv(dev);
|
|
|
@@ -811,19 +968,19 @@ static int m_can_set_bittiming(struct net_device *dev)
|
|
|
sjw = bt->sjw - 1;
|
|
|
tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
|
|
|
tseg2 = bt->phase_seg2 - 1;
|
|
|
- reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
|
|
|
- (tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
|
|
|
- m_can_write(priv, M_CAN_BTP, reg_btp);
|
|
|
+ reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
|
|
|
+ (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT);
|
|
|
+ m_can_write(priv, M_CAN_NBTP, reg_btp);
|
|
|
|
|
|
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
|
|
|
brp = dbt->brp - 1;
|
|
|
sjw = dbt->sjw - 1;
|
|
|
tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
|
|
|
tseg2 = dbt->phase_seg2 - 1;
|
|
|
- reg_btp = (brp << FBTR_FBRP_SHIFT) | (sjw << FBTR_FSJW_SHIFT) |
|
|
|
- (tseg1 << FBTR_FTSEG1_SHIFT) |
|
|
|
- (tseg2 << FBTR_FTSEG2_SHIFT);
|
|
|
- m_can_write(priv, M_CAN_FBTP, reg_btp);
|
|
|
+ reg_btp = (brp << DBTP_DBRP_SHIFT) | (sjw << DBTP_DSJW_SHIFT) |
|
|
|
+ (tseg1 << DBTP_DTSEG1_SHIFT) |
|
|
|
+ (tseg2 << DBTP_DTSEG2_SHIFT);
|
|
|
+ m_can_write(priv, M_CAN_DBTP, reg_btp);
|
|
|
}
|
|
|
|
|
|
return 0;
|
|
|
@@ -834,6 +991,7 @@ static int m_can_set_bittiming(struct net_device *dev)
|
|
|
* - configure rx fifo
|
|
|
* - accept non-matching frame into fifo 0
|
|
|
* - configure tx buffer
|
|
|
+ * - >= v3.1.x: TX FIFO is used
|
|
|
* - configure mode
|
|
|
* - setup bittiming
|
|
|
*/
|
|
|
@@ -850,49 +1008,89 @@ static void m_can_chip_config(struct net_device *dev)
|
|
|
/* Accept Non-matching Frames Into FIFO 0 */
|
|
|
m_can_write(priv, M_CAN_GFC, 0x0);
|
|
|
|
|
|
- /* only support one Tx Buffer currently */
|
|
|
- m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) |
|
|
|
- priv->mcfg[MRAM_TXB].off);
|
|
|
+ if (priv->version == 30) {
|
|
|
+ /* only support one Tx Buffer currently */
|
|
|
+ m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
|
|
|
+ priv->mcfg[MRAM_TXB].off);
|
|
|
+ } else {
|
|
|
+ /* TX FIFO is used for newer IP Core versions */
|
|
|
+ m_can_write(priv, M_CAN_TXBC,
|
|
|
+ (priv->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) |
|
|
|
+ (priv->mcfg[MRAM_TXB].off));
|
|
|
+ }
|
|
|
|
|
|
/* support 64 bytes payload */
|
|
|
m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
|
|
|
|
|
|
- m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) |
|
|
|
- priv->mcfg[MRAM_TXE].off);
|
|
|
+ /* TX Event FIFO */
|
|
|
+ if (priv->version == 30) {
|
|
|
+ m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
|
|
|
+ priv->mcfg[MRAM_TXE].off);
|
|
|
+ } else {
|
|
|
+ /* Full TX Event FIFO is used */
|
|
|
+ m_can_write(priv, M_CAN_TXEFC,
|
|
|
+ ((priv->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
|
|
|
+ & TXEFC_EFS_MASK) |
|
|
|
+ priv->mcfg[MRAM_TXE].off);
|
|
|
+ }
|
|
|
|
|
|
/* rx fifo configuration, blocking mode, fifo size 1 */
|
|
|
m_can_write(priv, M_CAN_RXF0C,
|
|
|
- (priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) |
|
|
|
- RXFC_FWM_1 | priv->mcfg[MRAM_RXF0].off);
|
|
|
+ (priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
|
|
|
+ priv->mcfg[MRAM_RXF0].off);
|
|
|
|
|
|
m_can_write(priv, M_CAN_RXF1C,
|
|
|
- (priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) |
|
|
|
- RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off);
|
|
|
+ (priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
|
|
|
+ priv->mcfg[MRAM_RXF1].off);
|
|
|
|
|
|
cccr = m_can_read(priv, M_CAN_CCCR);
|
|
|
- cccr &= ~(CCCR_TEST | CCCR_MON | (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
|
|
|
- (CCCR_CME_MASK << CCCR_CME_SHIFT));
|
|
|
test = m_can_read(priv, M_CAN_TEST);
|
|
|
test &= ~TEST_LBCK;
|
|
|
+ if (priv->version == 30) {
|
|
|
+ /* Version 3.0.x */
|
|
|
|
|
|
- if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
|
|
|
- cccr |= CCCR_MON;
|
|
|
+ cccr &= ~(CCCR_TEST | CCCR_MON |
|
|
|
+ (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
|
|
|
+ (CCCR_CME_MASK << CCCR_CME_SHIFT));
|
|
|
+
|
|
|
+ if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
|
|
|
+ cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
|
|
|
+
|
|
|
+ } else {
|
|
|
+ /* Version 3.1.x or 3.2.x */
|
|
|
+ cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE);
|
|
|
|
|
|
+ /* Only 3.2.x has NISO Bit implemented */
|
|
|
+ if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
|
|
|
+ cccr |= CCCR_NISO;
|
|
|
+
|
|
|
+ if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
|
|
|
+ cccr |= (CCCR_BRSE | CCCR_FDOE);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Loopback Mode */
|
|
|
if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
|
|
|
- cccr |= CCCR_TEST;
|
|
|
+ cccr |= CCCR_TEST | CCCR_MON;
|
|
|
test |= TEST_LBCK;
|
|
|
}
|
|
|
|
|
|
- if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
|
|
|
- cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
|
|
|
+ /* Enable Monitoring (all versions) */
|
|
|
+ if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
|
|
|
+ cccr |= CCCR_MON;
|
|
|
|
|
|
+ /* Write config */
|
|
|
m_can_write(priv, M_CAN_CCCR, cccr);
|
|
|
m_can_write(priv, M_CAN_TEST, test);
|
|
|
|
|
|
- /* enable interrupts */
|
|
|
+ /* Enable interrupts */
|
|
|
m_can_write(priv, M_CAN_IR, IR_ALL_INT);
|
|
|
if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
|
|
|
- m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC);
|
|
|
+ if (priv->version == 30)
|
|
|
+ m_can_write(priv, M_CAN_IE, IR_ALL_INT &
|
|
|
+ ~(IR_ERR_LEC_30X));
|
|
|
+ else
|
|
|
+ m_can_write(priv, M_CAN_IE, IR_ALL_INT &
|
|
|
+ ~(IR_ERR_LEC_31X));
|
|
|
else
|
|
|
m_can_write(priv, M_CAN_IE, IR_ALL_INT);
|
|
|
|
|
|
@@ -936,33 +1134,140 @@ static void free_m_can_dev(struct net_device *dev)
|
|
|
free_candev(dev);
|
|
|
}
|
|
|
|
|
|
-static struct net_device *alloc_m_can_dev(void)
|
|
|
+/* Checks core release number of M_CAN
|
|
|
+ * returns 0 if an unsupported device is detected
|
|
|
+ * else it returns the release and step coded as:
|
|
|
+ * return value = 10 * <release> + 1 * <step>
|
|
|
+ */
|
|
|
+static int m_can_check_core_release(void __iomem *m_can_base)
|
|
|
+{
|
|
|
+ u32 crel_reg;
|
|
|
+ u8 rel;
|
|
|
+ u8 step;
|
|
|
+ int res;
|
|
|
+ struct m_can_priv temp_priv = {
|
|
|
+ .base = m_can_base
|
|
|
+ };
|
|
|
+
|
|
|
+ /* Read Core Release Version and split into version number
|
|
|
+ * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
|
|
|
+ */
|
|
|
+ crel_reg = m_can_read(&temp_priv, M_CAN_CREL);
|
|
|
+ rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
|
|
|
+ step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
|
|
|
+
|
|
|
+ if (rel == 3) {
|
|
|
+ /* M_CAN v3.x.y: create return value */
|
|
|
+ res = 30 + step;
|
|
|
+ } else {
|
|
|
+ /* Unsupported M_CAN version */
|
|
|
+ res = 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ return res;
|
|
|
+}
|
|
|
+
|
|
|
+/* Selectable Non ISO support only in version 3.2.x
|
|
|
+ * This function checks if the bit is writable.
|
|
|
+ */
|
|
|
+static bool m_can_niso_supported(const struct m_can_priv *priv)
|
|
|
+{
|
|
|
+ u32 cccr_reg, cccr_poll;
|
|
|
+ int niso_timeout;
|
|
|
+
|
|
|
+ m_can_config_endisable(priv, true);
|
|
|
+ cccr_reg = m_can_read(priv, M_CAN_CCCR);
|
|
|
+ cccr_reg |= CCCR_NISO;
|
|
|
+ m_can_write(priv, M_CAN_CCCR, cccr_reg);
|
|
|
+
|
|
|
+ niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll,
|
|
|
+ (cccr_poll == cccr_reg), 0, 10);
|
|
|
+
|
|
|
+ /* Clear NISO */
|
|
|
+ cccr_reg &= ~(CCCR_NISO);
|
|
|
+ m_can_write(priv, M_CAN_CCCR, cccr_reg);
|
|
|
+
|
|
|
+ m_can_config_endisable(priv, false);
|
|
|
+
|
|
|
+ /* return false if time out (-ETIMEDOUT), else return true */
|
|
|
+ return !niso_timeout;
|
|
|
+}
|
|
|
+
|
|
|
+static struct net_device *alloc_m_can_dev(struct platform_device *pdev,
|
|
|
+ void __iomem *addr, u32 tx_fifo_size)
|
|
|
{
|
|
|
struct net_device *dev;
|
|
|
struct m_can_priv *priv;
|
|
|
+ int m_can_version;
|
|
|
+ unsigned int echo_buffer_count;
|
|
|
+
|
|
|
+ m_can_version = m_can_check_core_release(addr);
|
|
|
+ /* return if unsupported version */
|
|
|
+ if (!m_can_version) {
|
|
|
+ dev = NULL;
|
|
|
+ goto return_dev;
|
|
|
+ }
|
|
|
|
|
|
- dev = alloc_candev(sizeof(*priv), 1);
|
|
|
- if (!dev)
|
|
|
- return NULL;
|
|
|
+ /* If version < 3.1.x, then only one echo buffer is used */
|
|
|
+ echo_buffer_count = ((m_can_version == 30)
|
|
|
+ ? 1U
|
|
|
+ : (unsigned int)tx_fifo_size);
|
|
|
|
|
|
+ dev = alloc_candev(sizeof(*priv), echo_buffer_count);
|
|
|
+ if (!dev) {
|
|
|
+ dev = NULL;
|
|
|
+ goto return_dev;
|
|
|
+ }
|
|
|
priv = netdev_priv(dev);
|
|
|
netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
|
|
|
|
|
|
+ /* Shared properties of all M_CAN versions */
|
|
|
+ priv->version = m_can_version;
|
|
|
priv->dev = dev;
|
|
|
- priv->can.bittiming_const = &m_can_bittiming_const;
|
|
|
- priv->can.data_bittiming_const = &m_can_data_bittiming_const;
|
|
|
+ priv->base = addr;
|
|
|
priv->can.do_set_mode = m_can_set_mode;
|
|
|
priv->can.do_get_berr_counter = m_can_get_berr_counter;
|
|
|
|
|
|
- /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.1 */
|
|
|
- can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
|
|
|
-
|
|
|
- /* CAN_CTRLMODE_FD_NON_ISO can not be changed with M_CAN IP v3.0.1 */
|
|
|
+ /* Set M_CAN supported operations */
|
|
|
priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
|
|
|
CAN_CTRLMODE_LISTENONLY |
|
|
|
CAN_CTRLMODE_BERR_REPORTING |
|
|
|
CAN_CTRLMODE_FD;
|
|
|
|
|
|
+ /* Set properties depending on M_CAN version */
|
|
|
+ switch (priv->version) {
|
|
|
+ case 30:
|
|
|
+ /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
|
|
|
+ can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
|
|
|
+ priv->can.bittiming_const = &m_can_bittiming_const_30X;
|
|
|
+ priv->can.data_bittiming_const =
|
|
|
+ &m_can_data_bittiming_const_30X;
|
|
|
+ break;
|
|
|
+ case 31:
|
|
|
+ /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
|
|
|
+ can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
|
|
|
+ priv->can.bittiming_const = &m_can_bittiming_const_31X;
|
|
|
+ priv->can.data_bittiming_const =
|
|
|
+ &m_can_data_bittiming_const_31X;
|
|
|
+ break;
|
|
|
+ case 32:
|
|
|
+ priv->can.bittiming_const = &m_can_bittiming_const_31X;
|
|
|
+ priv->can.data_bittiming_const =
|
|
|
+ &m_can_data_bittiming_const_31X;
|
|
|
+ priv->can.ctrlmode_supported |= (m_can_niso_supported(priv)
|
|
|
+ ? CAN_CTRLMODE_FD_NON_ISO
|
|
|
+ : 0);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ /* Unsupported device: free candev */
|
|
|
+ free_m_can_dev(dev);
|
|
|
+ dev_err(&pdev->dev, "Unsupported version number: %2d",
|
|
|
+ priv->version);
|
|
|
+ dev = NULL;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+return_dev:
|
|
|
return dev;
|
|
|
}
|
|
|
|
|
|
@@ -1040,19 +1345,34 @@ static int m_can_close(struct net_device *dev)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
+static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
|
|
|
+{
|
|
|
+ struct m_can_priv *priv = netdev_priv(dev);
|
|
|
+ /*get wrap around for loopback skb index */
|
|
|
+ unsigned int wrap = priv->can.echo_skb_max;
|
|
|
+ int next_idx;
|
|
|
+
|
|
|
+ /* calculate next index */
|
|
|
+ next_idx = (++putidx >= wrap ? 0 : putidx);
|
|
|
+
|
|
|
+ /* check if occupied */
|
|
|
+ return !!priv->can.echo_skb[next_idx];
|
|
|
+}
|
|
|
+
|
|
|
static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
|
|
|
struct net_device *dev)
|
|
|
{
|
|
|
struct m_can_priv *priv = netdev_priv(dev);
|
|
|
struct canfd_frame *cf = (struct canfd_frame *)skb->data;
|
|
|
- u32 id, cccr;
|
|
|
+ u32 id, cccr, fdflags;
|
|
|
int i;
|
|
|
+ int putidx;
|
|
|
|
|
|
if (can_dropped_invalid_skb(dev, skb))
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
|
- netif_stop_queue(dev);
|
|
|
-
|
|
|
+ /* Generate ID field for TX buffer Element */
|
|
|
+ /* Common to all supported M_CAN versions */
|
|
|
if (cf->can_id & CAN_EFF_FLAG) {
|
|
|
id = cf->can_id & CAN_EFF_MASK;
|
|
|
id |= TX_BUF_XTD;
|
|
|
@@ -1063,33 +1383,93 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
|
|
|
if (cf->can_id & CAN_RTR_FLAG)
|
|
|
id |= TX_BUF_RTR;
|
|
|
|
|
|
- /* message ram configuration */
|
|
|
- m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
|
|
|
- m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len) << 16);
|
|
|
+ if (priv->version == 30) {
|
|
|
+ netif_stop_queue(dev);
|
|
|
|
|
|
- for (i = 0; i < cf->len; i += 4)
|
|
|
- m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4),
|
|
|
- *(u32 *)(cf->data + i));
|
|
|
+ /* message ram configuration */
|
|
|
+ m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
|
|
|
+ m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
|
|
|
+ can_len2dlc(cf->len) << 16);
|
|
|
|
|
|
- can_put_echo_skb(skb, dev, 0);
|
|
|
+ for (i = 0; i < cf->len; i += 4)
|
|
|
+ m_can_fifo_write(priv, 0,
|
|
|
+ M_CAN_FIFO_DATA(i / 4),
|
|
|
+ *(u32 *)(cf->data + i));
|
|
|
+
|
|
|
+ can_put_echo_skb(skb, dev, 0);
|
|
|
+
|
|
|
+ if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
|
|
|
+ cccr = m_can_read(priv, M_CAN_CCCR);
|
|
|
+ cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
|
|
|
+ if (can_is_canfd_skb(skb)) {
|
|
|
+ if (cf->flags & CANFD_BRS)
|
|
|
+ cccr |= CCCR_CMR_CANFD_BRS <<
|
|
|
+ CCCR_CMR_SHIFT;
|
|
|
+ else
|
|
|
+ cccr |= CCCR_CMR_CANFD <<
|
|
|
+ CCCR_CMR_SHIFT;
|
|
|
+ } else {
|
|
|
+ cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
|
|
|
+ }
|
|
|
+ m_can_write(priv, M_CAN_CCCR, cccr);
|
|
|
+ }
|
|
|
+ m_can_write(priv, M_CAN_TXBTIE, 0x1);
|
|
|
+ m_can_write(priv, M_CAN_TXBAR, 0x1);
|
|
|
+ /* End of xmit function for version 3.0.x */
|
|
|
+ } else {
|
|
|
+ /* Transmit routine for version >= v3.1.x */
|
|
|
+
|
|
|
+ /* Check if FIFO full */
|
|
|
+ if (m_can_tx_fifo_full(priv)) {
|
|
|
+ /* This shouldn't happen */
|
|
|
+ netif_stop_queue(dev);
|
|
|
+ netdev_warn(dev,
|
|
|
+ "TX queue active although FIFO is full.");
|
|
|
+ return NETDEV_TX_BUSY;
|
|
|
+ }
|
|
|
|
|
|
- if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
|
|
|
- cccr = m_can_read(priv, M_CAN_CCCR);
|
|
|
- cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
|
|
|
+ /* get put index for frame */
|
|
|
+ putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
|
|
|
+ >> TXFQS_TFQPI_SHIFT);
|
|
|
+ /* Write ID Field to FIFO Element */
|
|
|
+ m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
|
|
|
+
|
|
|
+ /* get CAN FD configuration of frame */
|
|
|
+ fdflags = 0;
|
|
|
if (can_is_canfd_skb(skb)) {
|
|
|
+ fdflags |= TX_BUF_FDF;
|
|
|
if (cf->flags & CANFD_BRS)
|
|
|
- cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT;
|
|
|
- else
|
|
|
- cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT;
|
|
|
- } else {
|
|
|
- cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
|
|
|
+ fdflags |= TX_BUF_BRS;
|
|
|
}
|
|
|
- m_can_write(priv, M_CAN_CCCR, cccr);
|
|
|
- }
|
|
|
|
|
|
- /* enable first TX buffer to start transfer */
|
|
|
- m_can_write(priv, M_CAN_TXBTIE, 0x1);
|
|
|
- m_can_write(priv, M_CAN_TXBAR, 0x1);
|
|
|
+ /* Construct DLC Field. Also contains CAN-FD configuration
|
|
|
+ * use put index of fifo as message marker
|
|
|
+ * it is used in TX interrupt for
|
|
|
+ * sending the correct echo frame
|
|
|
+ */
|
|
|
+ m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
|
|
|
+ ((putidx << TX_BUF_MM_SHIFT) &
|
|
|
+ TX_BUF_MM_MASK) |
|
|
|
+ (can_len2dlc(cf->len) << 16) |
|
|
|
+ fdflags | TX_BUF_EFC);
|
|
|
+
|
|
|
+ for (i = 0; i < cf->len; i += 4)
|
|
|
+ m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
|
|
|
+ *(u32 *)(cf->data + i));
|
|
|
+
|
|
|
+ /* Push loopback echo.
|
|
|
+ * Will be looped back on TX interrupt based on message marker
|
|
|
+ */
|
|
|
+ can_put_echo_skb(skb, dev, putidx);
|
|
|
+
|
|
|
+ /* Enable TX FIFO element to start transfer */
|
|
|
+ m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
|
|
|
+
|
|
|
+ /* stop network queue if fifo full */
|
|
|
+ if (m_can_tx_fifo_full(priv) ||
|
|
|
+ m_can_next_echo_skb_occupied(dev, putidx))
|
|
|
+ netif_stop_queue(dev);
|
|
|
+ }
|
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
}
|
|
|
@@ -1109,55 +1489,37 @@ static int register_m_can_dev(struct net_device *dev)
|
|
|
return register_candev(dev);
|
|
|
}
|
|
|
|
|
|
-static int m_can_of_parse_mram(struct platform_device *pdev,
|
|
|
- struct m_can_priv *priv)
|
|
|
+static void m_can_of_parse_mram(struct m_can_priv *priv,
|
|
|
+ const u32 *mram_config_vals)
|
|
|
{
|
|
|
- struct device_node *np = pdev->dev.of_node;
|
|
|
- struct resource *res;
|
|
|
- void __iomem *addr;
|
|
|
- u32 out_val[MRAM_CFG_LEN];
|
|
|
- int i, start, end, ret;
|
|
|
+ int i, start, end;
|
|
|
|
|
|
- /* message ram could be shared */
|
|
|
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
|
|
|
- if (!res)
|
|
|
- return -ENODEV;
|
|
|
-
|
|
|
- addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
|
|
- if (!addr)
|
|
|
- return -ENOMEM;
|
|
|
-
|
|
|
- /* get message ram configuration */
|
|
|
- ret = of_property_read_u32_array(np, "bosch,mram-cfg",
|
|
|
- out_val, sizeof(out_val) / 4);
|
|
|
- if (ret) {
|
|
|
- dev_err(&pdev->dev, "can not get message ram configuration\n");
|
|
|
- return -ENODEV;
|
|
|
- }
|
|
|
-
|
|
|
- priv->mram_base = addr;
|
|
|
- priv->mcfg[MRAM_SIDF].off = out_val[0];
|
|
|
- priv->mcfg[MRAM_SIDF].num = out_val[1];
|
|
|
+ priv->mcfg[MRAM_SIDF].off = mram_config_vals[0];
|
|
|
+ priv->mcfg[MRAM_SIDF].num = mram_config_vals[1];
|
|
|
priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
|
|
|
priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
|
|
|
- priv->mcfg[MRAM_XIDF].num = out_val[2];
|
|
|
+ priv->mcfg[MRAM_XIDF].num = mram_config_vals[2];
|
|
|
priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
|
|
|
priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
|
|
|
- priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK;
|
|
|
+ priv->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
|
|
|
+ (RXFC_FS_MASK >> RXFC_FS_SHIFT);
|
|
|
priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
|
|
|
priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
|
|
|
- priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK;
|
|
|
+ priv->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
|
|
|
+ (RXFC_FS_MASK >> RXFC_FS_SHIFT);
|
|
|
priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
|
|
|
priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
|
|
|
- priv->mcfg[MRAM_RXB].num = out_val[5];
|
|
|
+ priv->mcfg[MRAM_RXB].num = mram_config_vals[5];
|
|
|
priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
|
|
|
priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
|
|
|
- priv->mcfg[MRAM_TXE].num = out_val[6];
|
|
|
+ priv->mcfg[MRAM_TXE].num = mram_config_vals[6];
|
|
|
priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
|
|
|
priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
|
|
|
- priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK;
|
|
|
+ priv->mcfg[MRAM_TXB].num = mram_config_vals[7] &
|
|
|
+ (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
|
|
|
|
|
|
- dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
|
|
|
+ dev_dbg(priv->device,
|
|
|
+ "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
|
|
|
priv->mram_base,
|
|
|
priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
|
|
|
priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
|
|
|
@@ -1176,7 +1538,6 @@ static int m_can_of_parse_mram(struct platform_device *pdev,
|
|
|
for (i = start; i < end; i += 4)
|
|
|
writel(0x0, priv->mram_base + i);
|
|
|
|
|
|
- return 0;
|
|
|
}
|
|
|
|
|
|
static int m_can_plat_probe(struct platform_device *pdev)
|
|
|
@@ -1185,38 +1546,86 @@ static int m_can_plat_probe(struct platform_device *pdev)
|
|
|
struct m_can_priv *priv;
|
|
|
struct resource *res;
|
|
|
void __iomem *addr;
|
|
|
+ void __iomem *mram_addr;
|
|
|
struct clk *hclk, *cclk;
|
|
|
int irq, ret;
|
|
|
+ struct device_node *np;
|
|
|
+ u32 mram_config_vals[MRAM_CFG_LEN];
|
|
|
+ u32 tx_fifo_size;
|
|
|
+
|
|
|
+ np = pdev->dev.of_node;
|
|
|
|
|
|
hclk = devm_clk_get(&pdev->dev, "hclk");
|
|
|
cclk = devm_clk_get(&pdev->dev, "cclk");
|
|
|
+
|
|
|
if (IS_ERR(hclk) || IS_ERR(cclk)) {
|
|
|
- dev_err(&pdev->dev, "no clock find\n");
|
|
|
- return -ENODEV;
|
|
|
+ dev_err(&pdev->dev, "no clock found\n");
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto failed_ret;
|
|
|
}
|
|
|
|
|
|
+ /* Enable clocks. Necessary to read Core Release in order to determine
|
|
|
+ * M_CAN version
|
|
|
+ */
|
|
|
+ ret = clk_prepare_enable(hclk);
|
|
|
+ if (ret)
|
|
|
+ goto disable_hclk_ret;
|
|
|
+
|
|
|
+ ret = clk_prepare_enable(cclk);
|
|
|
+ if (ret)
|
|
|
+ goto disable_cclk_ret;
|
|
|
+
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
|
|
|
addr = devm_ioremap_resource(&pdev->dev, res);
|
|
|
irq = platform_get_irq_byname(pdev, "int0");
|
|
|
- if (IS_ERR(addr) || irq < 0)
|
|
|
- return -EINVAL;
|
|
|
|
|
|
- /* allocate the m_can device */
|
|
|
- dev = alloc_m_can_dev();
|
|
|
- if (!dev)
|
|
|
- return -ENOMEM;
|
|
|
+ if (IS_ERR(addr) || irq < 0) {
|
|
|
+ ret = -EINVAL;
|
|
|
+ goto disable_cclk_ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* message ram could be shared */
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
|
|
|
+ if (!res) {
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto disable_cclk_ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
|
|
+ if (!mram_addr) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto disable_cclk_ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* get message ram configuration */
|
|
|
+ ret = of_property_read_u32_array(np, "bosch,mram-cfg",
|
|
|
+ mram_config_vals,
|
|
|
+ sizeof(mram_config_vals) / 4);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&pdev->dev, "Could not get Message RAM configuration.");
|
|
|
+ goto disable_cclk_ret;
|
|
|
+ }
|
|
|
|
|
|
+ /* Get TX FIFO size
|
|
|
+ * Defines the total amount of echo buffers for loopback
|
|
|
+ */
|
|
|
+ tx_fifo_size = mram_config_vals[7];
|
|
|
+
|
|
|
+ /* allocate the m_can device */
|
|
|
+ dev = alloc_m_can_dev(pdev, addr, tx_fifo_size);
|
|
|
+ if (!dev) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto disable_cclk_ret;
|
|
|
+ }
|
|
|
priv = netdev_priv(dev);
|
|
|
dev->irq = irq;
|
|
|
- priv->base = addr;
|
|
|
priv->device = &pdev->dev;
|
|
|
priv->hclk = hclk;
|
|
|
priv->cclk = cclk;
|
|
|
priv->can.clock.freq = clk_get_rate(cclk);
|
|
|
+ priv->mram_base = mram_addr;
|
|
|
|
|
|
- ret = m_can_of_parse_mram(pdev, priv);
|
|
|
- if (ret)
|
|
|
- goto failed_free_dev;
|
|
|
+ m_can_of_parse_mram(priv, mram_config_vals);
|
|
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
@@ -1230,13 +1639,22 @@ static int m_can_plat_probe(struct platform_device *pdev)
|
|
|
|
|
|
devm_can_led_init(dev);
|
|
|
|
|
|
- dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
|
|
|
- KBUILD_MODNAME, priv->base, dev->irq);
|
|
|
+ dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n",
|
|
|
+ KBUILD_MODNAME, dev->irq, priv->version);
|
|
|
|
|
|
- return 0;
|
|
|
+ /* Probe finished
|
|
|
+ * Stop clocks. They will be reactivated once the M_CAN device is opened
|
|
|
+ */
|
|
|
+
|
|
|
+ goto disable_cclk_ret;
|
|
|
|
|
|
failed_free_dev:
|
|
|
free_m_can_dev(dev);
|
|
|
+disable_cclk_ret:
|
|
|
+ clk_disable_unprepare(cclk);
|
|
|
+disable_hclk_ret:
|
|
|
+ clk_disable_unprepare(hclk);
|
|
|
+failed_ret:
|
|
|
return ret;
|
|
|
}
|
|
|
|