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@@ -246,10 +246,6 @@
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#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
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#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
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-/* Intel Model 6 */
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-#define MSR_P6_EVNTSEL0 0x00000186
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-#define MSR_P6_EVNTSEL1 0x00000187
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-
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/* P4/Xeon+ specific */
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/* P4/Xeon+ specific */
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#define MSR_IA32_MCG_EAX 0x00000180
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#define MSR_IA32_MCG_EAX 0x00000180
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#define MSR_IA32_MCG_EBX 0x00000181
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#define MSR_IA32_MCG_EBX 0x00000181
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