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@@ -0,0 +1,377 @@
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+/*
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+ * Driver code for Tegra's Legacy Interrupt Controller
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+ *
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+ * Author: Marc Zyngier <marc.zyngier@arm.com>
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+ *
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+ * Heavily based on the original arch/arm/mach-tegra/irq.c code:
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+ * Copyright (C) 2011 Google, Inc.
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+ *
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+ * Author:
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+ * Colin Cross <ccross@android.com>
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+ *
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+ * Copyright (C) 2010,2013, NVIDIA Corporation
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+ *
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+ * This software is licensed under the terms of the GNU General Public
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+ * License version 2, as published by the Free Software Foundation, and
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+ * may be copied, distributed, and modified under those terms.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ */
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+
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+#include <linux/io.h>
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+#include <linux/irq.h>
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+#include <linux/irqdomain.h>
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+#include <linux/of_address.h>
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+#include <linux/slab.h>
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+#include <linux/syscore_ops.h>
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+
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+#include "irqchip.h"
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+
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+#define ICTLR_CPU_IEP_VFIQ 0x08
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+#define ICTLR_CPU_IEP_FIR 0x14
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+#define ICTLR_CPU_IEP_FIR_SET 0x18
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+#define ICTLR_CPU_IEP_FIR_CLR 0x1c
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+
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+#define ICTLR_CPU_IER 0x20
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+#define ICTLR_CPU_IER_SET 0x24
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+#define ICTLR_CPU_IER_CLR 0x28
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+#define ICTLR_CPU_IEP_CLASS 0x2C
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+
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+#define ICTLR_COP_IER 0x30
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+#define ICTLR_COP_IER_SET 0x34
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+#define ICTLR_COP_IER_CLR 0x38
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+#define ICTLR_COP_IEP_CLASS 0x3c
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+
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+#define TEGRA_MAX_NUM_ICTLRS 6
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+
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+static unsigned int num_ictlrs;
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+
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+struct tegra_ictlr_soc {
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+ unsigned int num_ictlrs;
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+};
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+
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+static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
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+ .num_ictlrs = 4,
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+};
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+
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+static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
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+ .num_ictlrs = 5,
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+};
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+
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+static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
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+ .num_ictlrs = 6,
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+};
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+
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+static const struct of_device_id ictlr_matches[] = {
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+ { .compatible = "nvidia,tegra210-ictlr", .data = &tegra210_ictlr_soc },
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+ { .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
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+ { .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
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+ { }
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+};
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+
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+struct tegra_ictlr_info {
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+ void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
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+#ifdef CONFIG_PM_SLEEP
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+ u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
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+ u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
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+ u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
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+ u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
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+
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+ u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
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+#endif
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+};
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+
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+static struct tegra_ictlr_info *lic;
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+
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+static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg)
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+{
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+ void __iomem *base = d->chip_data;
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+ u32 mask;
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+
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+ mask = BIT(d->hwirq % 32);
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+ writel_relaxed(mask, base + reg);
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+}
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+
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+static void tegra_mask(struct irq_data *d)
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+{
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+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
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+ irq_chip_mask_parent(d);
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+}
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+
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+static void tegra_unmask(struct irq_data *d)
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+{
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+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
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+ irq_chip_unmask_parent(d);
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+}
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+
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+static void tegra_eoi(struct irq_data *d)
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+{
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+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
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+ irq_chip_eoi_parent(d);
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+}
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+
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+static int tegra_retrigger(struct irq_data *d)
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+{
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+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
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+ return irq_chip_retrigger_hierarchy(d);
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+}
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+
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+#ifdef CONFIG_PM_SLEEP
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+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
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+{
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+ u32 irq = d->hwirq;
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+ u32 index, mask;
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+
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+ index = (irq / 32);
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+ mask = BIT(irq % 32);
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+ if (enable)
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+ lic->ictlr_wake_mask[index] |= mask;
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+ else
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+ lic->ictlr_wake_mask[index] &= ~mask;
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+
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+ /*
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+ * Do *not* call into the parent, as the GIC doesn't have any
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+ * wake-up facility...
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+ */
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+ return 0;
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+}
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+
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+static int tegra_ictlr_suspend(void)
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+{
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+ unsigned long flags;
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+ unsigned int i;
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+
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+ local_irq_save(flags);
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+ for (i = 0; i < num_ictlrs; i++) {
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+ void __iomem *ictlr = lic->base[i];
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+
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+ /* Save interrupt state */
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+ lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
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+ lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
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+ lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
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+ lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
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+
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+ /* Disable COP interrupts */
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+ writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
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+
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+ /* Disable CPU interrupts */
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+ writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
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+
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+ /* Enable the wakeup sources of ictlr */
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+ writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
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+ }
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+ local_irq_restore(flags);
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+
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+ return 0;
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+}
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+
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+static void tegra_ictlr_resume(void)
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+{
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+ unsigned long flags;
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+ unsigned int i;
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+
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+ local_irq_save(flags);
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+ for (i = 0; i < num_ictlrs; i++) {
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+ void __iomem *ictlr = lic->base[i];
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+
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+ writel_relaxed(lic->cpu_iep[i],
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+ ictlr + ICTLR_CPU_IEP_CLASS);
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+ writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
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+ writel_relaxed(lic->cpu_ier[i],
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+ ictlr + ICTLR_CPU_IER_SET);
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+ writel_relaxed(lic->cop_iep[i],
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+ ictlr + ICTLR_COP_IEP_CLASS);
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+ writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
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+ writel_relaxed(lic->cop_ier[i],
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+ ictlr + ICTLR_COP_IER_SET);
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+ }
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+ local_irq_restore(flags);
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+}
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+
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+static struct syscore_ops tegra_ictlr_syscore_ops = {
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+ .suspend = tegra_ictlr_suspend,
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+ .resume = tegra_ictlr_resume,
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+};
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+
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+static void tegra_ictlr_syscore_init(void)
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+{
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+ register_syscore_ops(&tegra_ictlr_syscore_ops);
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+}
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+#else
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+#define tegra_set_wake NULL
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+static inline void tegra_ictlr_syscore_init(void) {}
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+#endif
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+
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+static struct irq_chip tegra_ictlr_chip = {
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+ .name = "LIC",
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+ .irq_eoi = tegra_eoi,
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+ .irq_mask = tegra_mask,
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+ .irq_unmask = tegra_unmask,
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+ .irq_retrigger = tegra_retrigger,
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+ .irq_set_wake = tegra_set_wake,
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+ .flags = IRQCHIP_MASK_ON_SUSPEND,
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+#ifdef CONFIG_SMP
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+ .irq_set_affinity = irq_chip_set_affinity_parent,
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+#endif
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+};
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+
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+static int tegra_ictlr_domain_xlate(struct irq_domain *domain,
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+ struct device_node *controller,
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+ const u32 *intspec,
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+ unsigned int intsize,
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+ unsigned long *out_hwirq,
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+ unsigned int *out_type)
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+{
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+ if (domain->of_node != controller)
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+ return -EINVAL; /* Shouldn't happen, really... */
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+ if (intsize != 3)
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+ return -EINVAL; /* Not GIC compliant */
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+ if (intspec[0] != GIC_SPI)
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+ return -EINVAL; /* No PPI should point to this domain */
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+
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+ *out_hwirq = intspec[1];
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+ *out_type = intspec[2];
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+ return 0;
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+}
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+
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+static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
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+ unsigned int virq,
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+ unsigned int nr_irqs, void *data)
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+{
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+ struct of_phandle_args *args = data;
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+ struct of_phandle_args parent_args;
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+ struct tegra_ictlr_info *info = domain->host_data;
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+ irq_hw_number_t hwirq;
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+ unsigned int i;
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+
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+ if (args->args_count != 3)
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+ return -EINVAL; /* Not GIC compliant */
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+ if (args->args[0] != GIC_SPI)
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+ return -EINVAL; /* No PPI should point to this domain */
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+
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+ hwirq = args->args[1];
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+ if (hwirq >= (num_ictlrs * 32))
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+ return -EINVAL;
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+
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+ for (i = 0; i < nr_irqs; i++) {
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+ int ictlr = (hwirq + i) / 32;
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+
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+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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+ &tegra_ictlr_chip,
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+ &info->base[ictlr]);
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+ }
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+
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+ parent_args = *args;
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+ parent_args.np = domain->parent->of_node;
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+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
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+}
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+
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+static void tegra_ictlr_domain_free(struct irq_domain *domain,
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+ unsigned int virq,
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+ unsigned int nr_irqs)
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+{
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+ unsigned int i;
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+
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+ for (i = 0; i < nr_irqs; i++) {
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+ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
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+ irq_domain_reset_irq_data(d);
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+ }
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+}
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+
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+static const struct irq_domain_ops tegra_ictlr_domain_ops = {
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+ .xlate = tegra_ictlr_domain_xlate,
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+ .alloc = tegra_ictlr_domain_alloc,
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+ .free = tegra_ictlr_domain_free,
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+};
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+
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+static int __init tegra_ictlr_init(struct device_node *node,
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+ struct device_node *parent)
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+{
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+ struct irq_domain *parent_domain, *domain;
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+ const struct of_device_id *match;
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+ const struct tegra_ictlr_soc *soc;
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+ unsigned int i;
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+ int err;
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+
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+ if (!parent) {
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+ pr_err("%s: no parent, giving up\n", node->full_name);
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+ return -ENODEV;
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+ }
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+
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+ parent_domain = irq_find_host(parent);
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+ if (!parent_domain) {
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+ pr_err("%s: unable to obtain parent domain\n", node->full_name);
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+ return -ENXIO;
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+ }
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+
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+ match = of_match_node(ictlr_matches, node);
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+ if (!match) /* Should never happen... */
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+ return -ENODEV;
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+
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+ soc = match->data;
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+
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+ lic = kzalloc(sizeof(*lic), GFP_KERNEL);
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+ if (!lic)
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+ return -ENOMEM;
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+
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+ for (i = 0; i < TEGRA_MAX_NUM_ICTLRS; i++) {
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+ void __iomem *base;
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+
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+ base = of_iomap(node, i);
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+ if (!base)
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+ break;
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+
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+ lic->base[i] = base;
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+
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+ /* Disable all interrupts */
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+ writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
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+ /* All interrupts target IRQ */
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+ writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
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+
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+ num_ictlrs++;
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+ }
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+
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+ if (!num_ictlrs) {
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+ pr_err("%s: no valid regions, giving up\n", node->full_name);
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+ err = -ENOMEM;
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+ goto out_free;
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+ }
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+
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+ WARN(num_ictlrs != soc->num_ictlrs,
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+ "%s: Found %u interrupt controllers in DT; expected %u.\n",
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+ node->full_name, num_ictlrs, soc->num_ictlrs);
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+
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+
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+ domain = irq_domain_add_hierarchy(parent_domain, 0, num_ictlrs * 32,
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+ node, &tegra_ictlr_domain_ops,
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+ lic);
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+ if (!domain) {
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+ pr_err("%s: failed to allocated domain\n", node->full_name);
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+ err = -ENOMEM;
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+ goto out_unmap;
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+ }
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+
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+ tegra_ictlr_syscore_init();
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+
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+ pr_info("%s: %d interrupts forwarded to %s\n",
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+ node->full_name, num_ictlrs * 32, parent->full_name);
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+
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+ return 0;
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+
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+out_unmap:
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+ for (i = 0; i < num_ictlrs; i++)
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+ iounmap(lic->base[i]);
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+out_free:
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+ kfree(lic);
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+ return err;
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+}
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+
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+IRQCHIP_DECLARE(tegra20_ictlr, "nvidia,tegra20-ictlr", tegra_ictlr_init);
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+IRQCHIP_DECLARE(tegra30_ictlr, "nvidia,tegra30-ictlr", tegra_ictlr_init);
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+IRQCHIP_DECLARE(tegra210_ictlr, "nvidia,tegra210-ictlr", tegra_ictlr_init);
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Jason Cooper