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@@ -50,6 +50,9 @@ struct l2x0_regs l2x0_saved_regs;
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static bool of_init = false;
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+/*
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+ * Common code for all cache controllers.
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+ */
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static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
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{
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/* wait for cache operation by line or way to complete */
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@@ -67,6 +70,18 @@ static inline void l2c_set_debug(void __iomem *base, unsigned long val)
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outer_cache.set_debug(val);
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}
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+static inline void l2c_unlock(void __iomem *base, unsigned num)
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+{
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+ unsigned i;
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+
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+ for (i = 0; i < num; i++) {
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+ writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
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+ i * L2X0_LOCKDOWN_STRIDE);
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+ writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
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+ i * L2X0_LOCKDOWN_STRIDE);
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+ }
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+}
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+
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#ifdef CONFIG_CACHE_PL310
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static inline void cache_wait(void __iomem *reg, unsigned long mask)
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{
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@@ -308,7 +323,6 @@ static void l2x0_disable(void)
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static void l2x0_unlock(u32 cache_id)
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{
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int lockregs;
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- int i;
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switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
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case L2X0_CACHE_ID_PART_L310:
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@@ -323,12 +337,7 @@ static void l2x0_unlock(u32 cache_id)
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break;
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}
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- for (i = 0; i < lockregs; i++) {
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- writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
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- i * L2X0_LOCKDOWN_STRIDE);
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- writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
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- i * L2X0_LOCKDOWN_STRIDE);
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- }
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+ l2c_unlock(l2x0_base, lockregs);
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}
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void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
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