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arm: dra7: add DESHDCP clock

Add a new Linux clock for DRA7 based SoCs to control DESHDCP clock.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Tomi Valkeinen преди 10 години
родител
ревизия
2d5a3c803d
променени са 4 файла, в които са добавени 17 реда и са изтрити 0 реда
  1. 5 0
      arch/arm/boot/dts/dra7.dtsi
  2. 10 0
      arch/arm/boot/dts/dra7xx-clocks.dtsi
  3. 1 0
      arch/arm/mach-omap2/omap_hwmod_7xx_data.c
  4. 1 0
      drivers/clk/ti/clk-7xx.c

+ 5 - 0
arch/arm/boot/dts/dra7.dtsi

@@ -131,6 +131,11 @@
 							regulator-max-microvolt = <3000000>;
 							regulator-max-microvolt = <3000000>;
 						};
 						};
 					};
 					};
+
+					scm_conf_clocks: clocks {
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
 				};
 				};
 
 
 				dra7_pmx_core: pinmux@1400 {
 				dra7_pmx_core: pinmux@1400 {

+ 10 - 0
arch/arm/boot/dts/dra7xx-clocks.dtsi

@@ -2136,3 +2136,13 @@
 		clocks = <&dpll_usb_ck>;
 		clocks = <&dpll_usb_ck>;
 	};
 	};
 };
 };
+
+&scm_conf_clocks {
+	dss_deshdcp_clk: dss_deshdcp_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3_iclk_div>;
+		ti,bit-shift = <0>;
+		reg = <0x558>;
+	};
+};

+ 1 - 0
arch/arm/mach-omap2/omap_hwmod_7xx_data.c

@@ -438,6 +438,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 	{ .role = "video2_clk", .clk = "dss_video2_clk" },
 	{ .role = "video2_clk", .clk = "dss_video2_clk" },
 	{ .role = "video1_clk", .clk = "dss_video1_clk" },
 	{ .role = "video1_clk", .clk = "dss_video1_clk" },
 	{ .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 	{ .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
+	{ .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 };
 };
 
 
 static struct omap_hwmod dra7xx_dss_hwmod = {
 static struct omap_hwmod dra7xx_dss_hwmod = {

+ 1 - 0
drivers/clk/ti/clk-7xx.c

@@ -305,6 +305,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
 	DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
 	DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
 	DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
 	DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
 	DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
 	DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
+	DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),
 	{ .node_name = NULL },
 	{ .node_name = NULL },
 };
 };