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@@ -45,39 +45,6 @@
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#define CORE_EXPB0 0xb0
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-static int bcm7445_config_init(struct phy_device *phydev)
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-{
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- int ret;
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- const struct bcm7445_regs {
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- int reg;
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- u16 value;
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- } bcm7445_regs_cfg[] = {
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- /* increases ADC latency by 24ns */
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- { MII_BCM54XX_EXP_SEL, 0x0038 },
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- { MII_BCM54XX_EXP_DATA, 0xAB95 },
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- /* increases internal 1V LDO voltage by 5% */
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- { MII_BCM54XX_EXP_SEL, 0x2038 },
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- { MII_BCM54XX_EXP_DATA, 0xBB22 },
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- /* reduce RX low pass filter corner frequency */
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- { MII_BCM54XX_EXP_SEL, 0x6038 },
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- { MII_BCM54XX_EXP_DATA, 0xFFC5 },
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- /* reduce RX high pass filter corner frequency */
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- { MII_BCM54XX_EXP_SEL, 0x003a },
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- { MII_BCM54XX_EXP_DATA, 0x2002 },
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- };
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- unsigned int i;
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-
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- for (i = 0; i < ARRAY_SIZE(bcm7445_regs_cfg); i++) {
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- ret = phy_write(phydev,
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- bcm7445_regs_cfg[i].reg,
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- bcm7445_regs_cfg[i].value);
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- if (ret)
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- return ret;
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- }
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-
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- return 0;
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-}
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-
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static void phy_write_exp(struct phy_device *phydev,
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u16 reg, u16 value)
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{
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@@ -102,7 +69,7 @@ static void phy_write_misc(struct phy_device *phydev,
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phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
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}
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-static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
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+static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
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{
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/* Increase VCO range to prevent unlocking problem of PLL at low
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* temp
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@@ -204,12 +171,10 @@ static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
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dev_name(&phydev->dev), phydev->drv->name, rev, patch);
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switch (rev) {
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- case 0xa0:
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case 0xb0:
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- ret = bcm7445_config_init(phydev);
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+ ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
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break;
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default:
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- ret = bcm7xxx_28nm_afe_config_init(phydev);
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break;
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}
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@@ -337,7 +302,7 @@ static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
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.features = PHY_GBIT_FEATURES | \
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SUPPORTED_Pause | SUPPORTED_Asym_Pause, \
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.flags = PHY_IS_INTERNAL, \
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- .config_init = bcm7xxx_28nm_afe_config_init, \
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+ .config_init = bcm7xxx_28nm_config_init, \
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.config_aneg = genphy_config_aneg, \
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.read_status = genphy_read_status, \
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.resume = bcm7xxx_28nm_resume, \
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