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@@ -42,6 +42,66 @@ static void __init hsdk_init_per_cpu(unsigned int cpu)
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#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
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#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
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+#define HSDK_GPIO_INTC (ARC_PERIPHERAL_BASE + 0x3000)
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+
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+static void __init hsdk_enable_gpio_intc_wire(void)
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+{
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+ /*
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+ * Peripherals on CPU Card are wired to cpu intc via intermediate
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+ * DW APB GPIO blocks (mainly for debouncing)
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+ *
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+ * ---------------------
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+ * | snps,archs-intc |
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+ * ---------------------
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+ * |
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+ * ----------------------
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+ * | snps,archs-idu-intc |
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+ * ----------------------
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+ * | | | | |
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+ * | [eth] [USB] [... other peripherals]
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+ * |
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+ * -------------------
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+ * | snps,dw-apb-intc |
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+ * -------------------
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+ * | | | |
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+ * [Bt] [HAPS] [... other peripherals]
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+ *
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+ * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
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+ * with stacked INTCs. In particular problem happens if its master INTC
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+ * not yet instantiated. See discussion here -
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+ * https://lkml.org/lkml/2015/3/4/755
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+ *
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+ * So setup the first gpio block as a passive pass thru and hide it from
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+ * DT hardware topology - connect intc directly to cpu intc
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+ * The GPIO "wire" needs to be init nevertheless (here)
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+ *
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+ * One side adv is that peripheral interrupt handling avoids one nested
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+ * intc ISR hop
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+ *
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+ * According to HSDK User's Manual [1], "Table 2 Interrupt Mapping"
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+ * we have the following GPIO input lines used as sources of interrupt:
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+ * - GPIO[0] - Bluetooth interrupt of RS9113 module
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+ * - GPIO[2] - HAPS interrupt (on HapsTrak 3 connector)
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+ * - GPIO[3] - Audio codec (MAX9880A) interrupt
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+ * - GPIO[8-23] - Available on Arduino and PMOD_x headers
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+ * For now there's no use of Arduino and PMOD_x headers in Linux
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+ * use-case so we only enable lines 0, 2 and 3.
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+ *
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+ * [1] https://github.com/foss-for-synopsys-dwc-arc-processors/ARC-Development-Systems-Forum/wiki/docs/ARC_HSDK_User_Guide.pdf
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+ */
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+#define GPIO_INTEN (HSDK_GPIO_INTC + 0x30)
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+#define GPIO_INTMASK (HSDK_GPIO_INTC + 0x34)
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+#define GPIO_INTTYPE_LEVEL (HSDK_GPIO_INTC + 0x38)
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+#define GPIO_INT_POLARITY (HSDK_GPIO_INTC + 0x3c)
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+#define GPIO_INT_CONNECTED_MASK 0x0d
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+
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+ iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK);
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+ iowrite32(~GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTMASK);
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+ iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL);
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+ iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY);
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+ iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
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+}
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+
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static void __init hsdk_init_early(void)
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{
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/*
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@@ -62,6 +122,8 @@ static void __init hsdk_init_early(void)
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* minimum possible div-by-2.
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*/
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iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
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+
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+ hsdk_enable_gpio_intc_wire();
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}
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static const char *hsdk_compat[] __initconst = {
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