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@@ -124,7 +124,8 @@ static void mlx5e_update_carrier(struct mlx5e_priv *priv)
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u8 port_state;
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u8 port_state;
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port_state = mlx5_query_vport_state(mdev,
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port_state = mlx5_query_vport_state(mdev,
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- MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
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+ MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
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+ 0);
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if (port_state == VPORT_STATE_UP) {
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if (port_state == VPORT_STATE_UP) {
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netdev_info(priv->netdev, "Link up\n");
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netdev_info(priv->netdev, "Link up\n");
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@@ -243,18 +244,14 @@ static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
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mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
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mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
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}
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}
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-static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
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+static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
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{
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{
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struct mlx5e_pport_stats *pstats = &priv->stats.pport;
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struct mlx5e_pport_stats *pstats = &priv->stats.pport;
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struct mlx5_core_dev *mdev = priv->mdev;
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struct mlx5_core_dev *mdev = priv->mdev;
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+ u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
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int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
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int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
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int prio;
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int prio;
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void *out;
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void *out;
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- u32 *in;
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-
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- in = kvzalloc(sz, GFP_KERNEL);
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- if (!in)
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- return;
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MLX5_SET(ppcnt_reg, in, local_port, 1);
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MLX5_SET(ppcnt_reg, in, local_port, 1);
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@@ -262,6 +259,9 @@ static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
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MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
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MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
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+ if (!full)
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+ return;
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+
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out = pstats->RFC_2863_counters;
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out = pstats->RFC_2863_counters;
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MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
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MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
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@@ -287,52 +287,55 @@ static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
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mlx5_core_access_reg(mdev, in, sz, out, sz,
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mlx5_core_access_reg(mdev, in, sz, out, sz,
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MLX5_REG_PPCNT, 0, 0);
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MLX5_REG_PPCNT, 0, 0);
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}
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}
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-
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- kvfree(in);
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}
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}
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static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
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static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
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{
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{
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struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
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struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
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+ u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
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+ int err;
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if (!priv->q_counter)
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if (!priv->q_counter)
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return;
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return;
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- mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
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- &qcnt->rx_out_of_buffer);
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+ err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
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+ if (err)
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+ return;
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+
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+ qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
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}
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}
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static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
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static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
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{
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{
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struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
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struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
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struct mlx5_core_dev *mdev = priv->mdev;
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struct mlx5_core_dev *mdev = priv->mdev;
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+ u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
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int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
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int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
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void *out;
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void *out;
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- u32 *in;
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if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
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if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
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return;
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return;
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- in = kvzalloc(sz, GFP_KERNEL);
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- if (!in)
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- return;
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-
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out = pcie_stats->pcie_perf_counters;
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out = pcie_stats->pcie_perf_counters;
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MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
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MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
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-
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- kvfree(in);
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}
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}
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-void mlx5e_update_stats(struct mlx5e_priv *priv)
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+void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
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{
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{
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- mlx5e_update_pcie_counters(priv);
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- mlx5e_update_pport_counters(priv);
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+ if (full)
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+ mlx5e_update_pcie_counters(priv);
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+ mlx5e_update_pport_counters(priv, full);
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mlx5e_update_vport_counters(priv);
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mlx5e_update_vport_counters(priv);
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mlx5e_update_q_counter(priv);
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mlx5e_update_q_counter(priv);
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mlx5e_update_sw_counters(priv);
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mlx5e_update_sw_counters(priv);
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}
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}
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+static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
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+{
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+ mlx5e_update_stats(priv, false);
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+}
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+
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void mlx5e_update_stats_work(struct work_struct *work)
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void mlx5e_update_stats_work(struct work_struct *work)
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{
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{
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struct delayed_work *dwork = to_delayed_work(work);
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struct delayed_work *dwork = to_delayed_work(work);
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@@ -3067,7 +3070,6 @@ mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
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*/
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*/
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stats->multicast =
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stats->multicast =
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VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
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VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
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-
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}
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}
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static void mlx5e_set_rx_mode(struct net_device *dev)
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static void mlx5e_set_rx_mode(struct net_device *dev)
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@@ -3727,7 +3729,7 @@ static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
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if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
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if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
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mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
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mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
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if (!MLX5_CAP_GEN(mdev, cq_moderation))
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if (!MLX5_CAP_GEN(mdev, cq_moderation))
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- mlx5_core_warn(mdev, "CQ modiration is not supported\n");
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+ mlx5_core_warn(mdev, "CQ moderation is not supported\n");
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return 0;
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return 0;
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}
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}
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@@ -3860,7 +3862,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
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/* set CQE compression */
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/* set CQE compression */
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params->rx_cqe_compress_def = false;
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params->rx_cqe_compress_def = false;
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if (MLX5_CAP_GEN(mdev, cqe_compression) &&
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if (MLX5_CAP_GEN(mdev, cqe_compression) &&
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- MLX5_CAP_GEN(mdev, vport_group_manager))
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+ MLX5_CAP_GEN(mdev, vport_group_manager))
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params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
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params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
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MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
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MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
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@@ -4211,7 +4213,7 @@ static const struct mlx5e_profile mlx5e_nic_profile = {
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.cleanup_tx = mlx5e_cleanup_nic_tx,
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.cleanup_tx = mlx5e_cleanup_nic_tx,
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.enable = mlx5e_nic_enable,
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.enable = mlx5e_nic_enable,
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.disable = mlx5e_nic_disable,
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.disable = mlx5e_nic_disable,
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- .update_stats = mlx5e_update_stats,
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+ .update_stats = mlx5e_update_ndo_stats,
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.max_nch = mlx5e_get_max_num_channels,
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.max_nch = mlx5e_get_max_num_channels,
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.rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
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.rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
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.rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
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.rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
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