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@@ -20,9 +20,7 @@
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#include <linux/of_net.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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-#include <linux/reset.h>
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#include <linux/stmmac.h>
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-#include "stmmac.h"
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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@@ -36,7 +34,6 @@ struct socfpga_dwmac {
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u32 reg_shift;
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struct device *dev;
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struct regmap *sys_mgr_base_addr;
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- struct reset_control *stmmac_rst;
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};
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static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
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@@ -46,13 +43,6 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *
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u32 reg_offset, reg_shift;
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int ret;
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- dwmac->stmmac_rst = devm_reset_control_get(dev,
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- STMMAC_RESOURCE_NAME);
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- if (IS_ERR(dwmac->stmmac_rst)) {
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- dev_info(dev, "Could not get reset control!\n");
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- return -EINVAL;
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- }
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-
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dwmac->interface = of_get_phy_mode(np);
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sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
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@@ -135,65 +125,6 @@ static void *socfpga_dwmac_probe(struct platform_device *pdev)
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return dwmac;
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}
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-static void socfpga_dwmac_exit(struct platform_device *pdev, void *priv)
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-{
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- struct socfpga_dwmac *dwmac = priv;
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-
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- /* On socfpga platform exit, assert and hold reset to the
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- * enet controller - the default state after a hard reset.
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- */
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- if (dwmac->stmmac_rst)
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- reset_control_assert(dwmac->stmmac_rst);
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-}
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-
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-static int socfpga_dwmac_init(struct platform_device *pdev, void *priv)
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-{
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- struct socfpga_dwmac *dwmac = priv;
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- struct net_device *ndev = platform_get_drvdata(pdev);
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- struct stmmac_priv *stpriv = NULL;
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- int ret = 0;
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-
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- if (ndev)
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- stpriv = netdev_priv(ndev);
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-
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- /* Assert reset to the enet controller before changing the phy mode */
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- if (dwmac->stmmac_rst)
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- reset_control_assert(dwmac->stmmac_rst);
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-
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- /* Setup the phy mode in the system manager registers according to
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- * devicetree configuration
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- */
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- ret = socfpga_dwmac_setup(dwmac);
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-
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- /* Deassert reset for the phy configuration to be sampled by
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- * the enet controller, and operation to start in requested mode
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- */
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- if (dwmac->stmmac_rst)
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- reset_control_deassert(dwmac->stmmac_rst);
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-
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- /* Before the enet controller is suspended, the phy is suspended.
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- * This causes the phy clock to be gated. The enet controller is
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- * resumed before the phy, so the clock is still gated "off" when
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- * the enet controller is resumed. This code makes sure the phy
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- * is "resumed" before reinitializing the enet controller since
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- * the enet controller depends on an active phy clock to complete
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- * a DMA reset. A DMA reset will "time out" if executed
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- * with no phy clock input on the Synopsys enet controller.
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- * Verified through Synopsys Case #8000711656.
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- *
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- * Note that the phy clock is also gated when the phy is isolated.
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- * Phy "suspend" and "isolate" controls are located in phy basic
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- * control register 0, and can be modified by the phy driver
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- * framework.
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- */
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- if (stpriv && stpriv->phydev)
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- phy_resume(stpriv->phydev);
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-
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- return ret;
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-}
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-
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const struct stmmac_of_data socfpga_gmac_data = {
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.setup = socfpga_dwmac_probe,
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- .init = socfpga_dwmac_init,
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- .exit = socfpga_dwmac_exit,
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};
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