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@@ -485,7 +485,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
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WREG32(mmVM_L2_CNTL3, tmp);
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/* setup context0 */
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WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
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- WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
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+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1);
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WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
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WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
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(u32)(adev->dummy_page.addr >> 12));
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@@ -506,7 +506,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
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*/
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/* set vm size, must be a multiple of 4 */
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WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
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- WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn);
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+ WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
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for (i = 1; i < 16; i++) {
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if (i < 8)
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WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
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