|
@@ -49,14 +49,12 @@ static inline void __iomem *rk_base(struct clock_event_device *ce)
|
|
|
static inline void rk_timer_disable(struct clock_event_device *ce)
|
|
static inline void rk_timer_disable(struct clock_event_device *ce)
|
|
|
{
|
|
{
|
|
|
writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG);
|
|
writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG);
|
|
|
- dsb();
|
|
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
|
|
static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
|
|
|
{
|
|
{
|
|
|
writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
|
|
writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
|
|
|
rk_base(ce) + TIMER_CONTROL_REG);
|
|
rk_base(ce) + TIMER_CONTROL_REG);
|
|
|
- dsb();
|
|
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static void rk_timer_update_counter(unsigned long cycles,
|
|
static void rk_timer_update_counter(unsigned long cycles,
|
|
@@ -64,13 +62,11 @@ static void rk_timer_update_counter(unsigned long cycles,
|
|
|
{
|
|
{
|
|
|
writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
|
|
writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
|
|
|
writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
|
|
writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
|
|
|
- dsb();
|
|
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static void rk_timer_interrupt_clear(struct clock_event_device *ce)
|
|
static void rk_timer_interrupt_clear(struct clock_event_device *ce)
|
|
|
{
|
|
{
|
|
|
writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
|
|
writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
|
|
|
- dsb();
|
|
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static inline int rk_timer_set_next_event(unsigned long cycles,
|
|
static inline int rk_timer_set_next_event(unsigned long cycles,
|