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@@ -762,15 +762,36 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
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{
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const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
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- uint64_t cur_pe_start = ~0, cur_pe_end = ~0, cur_dst = ~0;
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+ uint64_t cur_pe_start, cur_pe_end, cur_dst;
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uint64_t addr; /* next GPU address to be updated */
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+ uint64_t pt_idx;
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+ struct amdgpu_bo *pt;
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+ unsigned nptes; /* next number of ptes to be updated */
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+ uint64_t next_pe_start;
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+
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+ /* initialize the variables */
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+ addr = start;
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+ pt_idx = addr >> amdgpu_vm_block_size;
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+ pt = vm->page_tables[pt_idx].entry.robj;
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+
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+ if ((addr & ~mask) == (end & ~mask))
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+ nptes = end - addr;
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+ else
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+ nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
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+
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+ cur_pe_start = amdgpu_bo_gpu_offset(pt);
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+ cur_pe_start += (addr & mask) * 8;
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+ cur_pe_end = cur_pe_start + 8 * nptes;
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+ cur_dst = dst;
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+
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+ /* for next ptb*/
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+ addr += nptes;
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+ dst += nptes * AMDGPU_GPU_PAGE_SIZE;
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/* walk over the address space and update the page tables */
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- for (addr = start; addr < end; ) {
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- uint64_t pt_idx = addr >> amdgpu_vm_block_size;
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- struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj;
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- unsigned nptes; /* next number of ptes to be updated */
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- uint64_t next_pe_start;
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+ while (addr < end) {
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+ pt_idx = addr >> amdgpu_vm_block_size;
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+ pt = vm->page_tables[pt_idx].entry.robj;
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if ((addr & ~mask) == (end & ~mask))
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nptes = end - addr;
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@@ -796,6 +817,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
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cur_dst = dst;
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}
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+ /* for next ptb*/
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addr += nptes;
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dst += nptes * AMDGPU_GPU_PAGE_SIZE;
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}
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