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@@ -0,0 +1,90 @@
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+Qualcomm MSM8660 TLMM block
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+
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+Required properties:
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+- compatible: "qcom,msm8660-pinctrl"
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+- reg: Should be the base address and length of the TLMM block.
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+- interrupts: Should be the parent IRQ of the TLMM block.
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+- interrupt-controller: Marks the device node as an interrupt controller.
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+- #interrupt-cells: Should be two.
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+- gpio-controller: Marks the device node as a GPIO controller.
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+- #gpio-cells : Should be two.
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+ The first cell is the gpio pin number and the
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+ second cell is used for optional parameters.
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+
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+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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+a general description of GPIO and interrupt bindings.
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+
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+Please refer to pinctrl-bindings.txt in this directory for details of the
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+common pinctrl bindings used by client devices, including the meaning of the
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+phrase "pin configuration node".
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+
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+Qualcomm's pin configuration nodes act as a container for an arbitrary number of
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+subnodes. Each of these subnodes represents some desired configuration for a
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+pin, a group, or a list of pins or groups. This configuration can include the
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+mux function to select on those pin(s)/group(s), and various pin configuration
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+parameters, such as pull-up, drive strength, etc.
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+
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+The name of each subnode is not important; all subnodes should be enumerated
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+and processed purely based on their content.
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+
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+Each subnode only affects those parameters that are explicitly listed. In
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+other words, a subnode that lists a mux function but no pin configuration
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+parameters implies no information about any pin configuration parameters.
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+Similarly, a pin subnode that describes a pullup parameter implies no
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+information about e.g. the mux function.
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+
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+
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+The following generic properties as defined in pinctrl-bindings.txt are valid
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+to specify in a pin configuration subnode:
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+
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+ pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
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+ output-low, output-high.
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+
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+Non-empty subnodes must specify the 'pins' property.
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+
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+Valid values for pins are:
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+ gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data
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+
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+Valid values for function are:
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+ gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b,
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+ gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n,
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+ gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
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+ gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n,
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+ gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s,
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+ lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1,
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+ usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm,
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+
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+Example:
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+
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+ msmgpio: pinctrl@800000 {
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+ compatible = "qcom,msm8660-pinctrl";
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+ reg = <0x800000 0x4000>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ interrupts = <0 16 0x4>;
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gsbi12_uart>;
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+
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+ gsbi12_uart: gsbi12-uart {
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+ mux {
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+ pins = "gpio117", "gpio118";
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+ function = "gsbi12";
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+ };
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+
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+ tx {
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+ pins = "gpio118";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ rx {
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+ pins = "gpio117";
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+ drive-strength = <2>;
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+ bias-pull-up;
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+ };
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+ };
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+ };
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