drm/amdgpu: extract pcie helpers to common header

These will be used by multiple powerplay drivers and
other IP modules.

Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/include/amd_pcie.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __AMD_PCIE_H__
+#define __AMD_PCIE_H__
+
+/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
+#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
+#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
+
+/* Following flags shows PCIe link speed supported by ASIC H/W.*/
+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
+
+/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
+
+#endif

drivers/gpu/drm/amd/include/amd_pcie_helpers.h

@@ -0,0 +1,141 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __AMD_PCIE_HELPERS_H__
+#define __AMD_PCIE_HELPERS_H__
+
+#include "amd_pcie.h"
+
+static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
+{
+	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+		return 1;
+
+	return 0;
+}
+
+static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
+{
+	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
+		return 1;
+
+	return 0;
+}
+
+/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
+static inline uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap,
+					    uint16_t ns_pcie_gen)
+{
+	uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
+		CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
+	uint32_t sys_pcie_link_speed_cap  = (pcie_link_speed_cap &
+		CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
+
+	switch (asic_pcie_link_speed_cap) {
+	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
+		return PP_PCIEGen1;
+
+	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
+		return PP_PCIEGen2;
+
+	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
+		return PP_PCIEGen3;
+
+	default:
+		if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
+			(ns_pcie_gen == PP_PCIEGen3)) {
+			return PP_PCIEGen3;
+		} else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
+			((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
+			return PP_PCIEGen2;
+		}
+	}
+
+	return PP_PCIEGen1;
+}
+
+static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap,
+					     uint16_t ns_pcie_lanes)
+{
+	int i, j;
+	uint16_t new_pcie_lanes = ns_pcie_lanes;
+	uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
+
+	switch (pcie_lane_width_cap) {
+	case 0:
+		printk(KERN_ERR "No valid PCIE lane width reported");
+		break;
+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
+		new_pcie_lanes = 1;
+		break;
+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
+		new_pcie_lanes = 2;
+		break;
+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
+		new_pcie_lanes = 4;
+		break;
+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
+		new_pcie_lanes = 8;
+		break;
+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
+		new_pcie_lanes = 12;
+		break;
+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
+		new_pcie_lanes = 16;
+		break;
+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
+		new_pcie_lanes = 32;
+		break;
+	default:
+		for (i = 0; i < 7; i++) {
+			if (ns_pcie_lanes == pcie_lanes[i]) {
+				if (pcie_lane_width_cap & (0x10000 << i)) {
+					break;
+				} else {
+					for (j = i - 1; j >= 0; j--) {
+						if (pcie_lane_width_cap & (0x10000 << j)) {
+							new_pcie_lanes = pcie_lanes[j];
+							break;
+						}
+					}
+
+					if (j < 0) {
+						for (j = i + 1; j < 7; j++) {
+							if (pcie_lane_width_cap & (0x10000 << j)) {
+								new_pcie_lanes = pcie_lanes[j];
+								break;
+							}
+						}
+						if (j > 7)
+							printk(KERN_ERR "Cannot find a valid PCIE lane width!");
+					}
+				}
+				break;
+			}
+		}
+		break;
+	}
+
+	return new_pcie_lanes;
+}
+
+#endif

drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c

@@ -49,6 +49,7 @@
 #include "tonga_pptable.h"
 #include "pp_debug.h"
 #include "pp_acpi.h"
+#include "amd_pcie_helpers.h"
 
 #define VOLTAGE_SCALE	4
 #define SMC_RAM_END		0x40000

drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h

@@ -339,8 +339,6 @@ enum Fiji_I2CLineID {
 extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
 extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
 extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
-extern uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen);
-extern uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes);
 
 #define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
 #define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)

drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c

@@ -53,6 +53,7 @@
 
 #include "cgs_linux.h"
 #include "eventmgr.h"
+#include "amd_pcie_helpers.h"
 
 #define MC_CG_ARB_FREQ_F0           0x0a
 #define MC_CG_ARB_FREQ_F1           0x0b
@@ -2651,117 +2652,6 @@ static void tonga_setup_pcie_table_entry(
 	dpm_table->dpm_levels[index].enabled = 1;
 }
 
-bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
-{
-	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-		return 1;
-
-	return 0;
-}
-
-bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
-{
-	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-		return 1;
-
-	return 0;
-}
-
-/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
-uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen)
-{
-	uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
-		CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
-	uint32_t sys_pcie_link_speed_cap  = (pcie_link_speed_cap &
-		CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
-
-	switch (asic_pcie_link_speed_cap) {
-	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
-		return PP_PCIEGen1;
-
-	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
-		return PP_PCIEGen2;
-
-	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
-		return PP_PCIEGen3;
-
-	default:
-		if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
-			(ns_pcie_gen == PP_PCIEGen3)) {
-			return PP_PCIEGen3;
-		} else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
-			((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
-			return PP_PCIEGen2;
-		}
-	}
-
-	return PP_PCIEGen1;
-}
-
-uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes)
-{
-	int i, j;
-	uint16_t new_pcie_lanes = ns_pcie_lanes;
-	uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
-
-	switch (pcie_lane_width_cap) {
-	case 0:
-		printk(KERN_ERR "[ powerplay ] No valid PCIE lane width reported by CAIL!");
-		break;
-	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
-		new_pcie_lanes = 1;
-		break;
-	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
-		new_pcie_lanes = 2;
-		break;
-	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
-		new_pcie_lanes = 4;
-		break;
-	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
-		new_pcie_lanes = 8;
-		break;
-	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
-		new_pcie_lanes = 12;
-		break;
-	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
-		new_pcie_lanes = 16;
-		break;
-	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
-		new_pcie_lanes = 32;
-		break;
-	default:
-		for (i = 0; i < 7; i++) {
-			if (ns_pcie_lanes == pcie_lanes[i]) {
-				if (pcie_lane_width_cap & (0x10000 << i)) {
-					break;
-				} else {
-					for (j = i - 1; j >= 0; j--) {
-						if (pcie_lane_width_cap & (0x10000 << j)) {
-							new_pcie_lanes = pcie_lanes[j];
-							break;
-						}
-					}
-
-					if (j < 0) {
-						for (j = i + 1; j < 7; j++) {
-							if (pcie_lane_width_cap & (0x10000 << j)) {
-								new_pcie_lanes = pcie_lanes[j];
-								break;
-							}
-						}
-						if (j > 7)
-							printk(KERN_ERR "[ powerplay ] Cannot find a valid PCIE lane width!");
-					}
-				}
-				break;
-			}
-		}
-		break;
-	}
-
-	return new_pcie_lanes;
-}
-
 static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
 {
 	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h

@@ -386,30 +386,6 @@ typedef struct tonga_hwmgr tonga_hwmgr;
 
 #define TONGA_UNUSED_GPIO_PIN                        0x7F
 
-/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
-#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
-#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
-#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
-#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
-#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
-
-/* Following flags shows PCIe link speed supported by ASIC H/W.*/
-#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
-#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
-#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
-#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
-#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
-
-/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
-#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
-#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
-#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
-#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
-#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
-#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
-#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
-#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
-
 #define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
 #define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)