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@@ -167,6 +167,18 @@
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status = "disabled";
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};
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+ i2c1: i2c@40005400 {
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+ compatible = "st,stm32f7-i2c";
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+ reg = <0x40005400 0x400>;
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+ interrupts = <31>,
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+ <32>;
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+ resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
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+ clocks = <&rcc 1 CLK_I2C1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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cec: cec@40006c00 {
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compatible = "st,stm32-cec";
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reg = <0x40006C00 0x400>;
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@@ -379,6 +391,16 @@
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bias-disable;
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};
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};
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+
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+ i2c1_pins_b: i2c1@0 {
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+ pins {
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+ pinmux = <STM32F746_PB9_FUNC_I2C1_SDA>,
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+ <STM32F746_PB8_FUNC_I2C1_SCL>;
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+ bias-disable;
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+ drive-open-drain;
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+ slew-rate = <0>;
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+ };
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+ };
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};
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crc: crc@40023000 {
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