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@@ -64,10 +64,10 @@ static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
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if (hsuc->direction == DMA_MEM_TO_DEV) {
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bsr = config->dst_maxburst;
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- mtsr = config->dst_addr_width;
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+ mtsr = config->src_addr_width;
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} else if (hsuc->direction == DMA_DEV_TO_MEM) {
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bsr = config->src_maxburst;
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- mtsr = config->src_addr_width;
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+ mtsr = config->dst_addr_width;
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}
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hsu_chan_disable(hsuc);
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@@ -135,7 +135,7 @@ static u32 hsu_dma_chan_get_sr(struct hsu_dma_chan *hsuc)
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sr = hsu_chan_readl(hsuc, HSU_CH_SR);
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spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
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- return sr;
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+ return sr & ~(HSU_CH_SR_DESCE_ANY | HSU_CH_SR_CDESC_ANY);
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}
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irqreturn_t hsu_dma_irq(struct hsu_dma_chip *chip, unsigned short nr)
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@@ -254,10 +254,13 @@ static void hsu_dma_issue_pending(struct dma_chan *chan)
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static size_t hsu_dma_active_desc_size(struct hsu_dma_chan *hsuc)
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{
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struct hsu_dma_desc *desc = hsuc->desc;
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- size_t bytes = desc->length;
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+ size_t bytes = 0;
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int i;
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- i = desc->active % HSU_DMA_CHAN_NR_DESC;
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+ for (i = desc->active; i < desc->nents; i++)
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+ bytes += desc->sg[i].len;
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+
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+ i = HSU_DMA_CHAN_NR_DESC - 1;
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do {
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bytes += hsu_chan_readl(hsuc, HSU_CH_DxTSR(i));
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} while (--i >= 0);
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