|
|
@@ -992,11 +992,13 @@ static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev,
|
|
|
{
|
|
|
uint32_t val = 0;
|
|
|
|
|
|
- if (state == AMDGPU_IRQ_STATE_ENABLE)
|
|
|
- val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
|
|
|
+ if (!amdgpu_sriov_vf(adev)) {
|
|
|
+ if (state == AMDGPU_IRQ_STATE_ENABLE)
|
|
|
+ val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
|
|
|
|
|
|
- WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
|
|
|
- ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
|
|
|
+ WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
|
|
|
+ ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
|
|
|
+ }
|
|
|
return 0;
|
|
|
}
|
|
|
|