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@@ -0,0 +1,622 @@
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+/* QLogic qedr NIC Driver
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+ * Copyright (c) 2015-2016 QLogic Corporation
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+ *
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+ * This software is available to you under a choice of one of two
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+ * licenses. You may choose to be licensed under the terms of the GNU
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+ * General Public License (GPL) Version 2, available from the file
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+ * COPYING in the main directory of this source tree, or the
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+ * OpenIB.org BSD license below:
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+ *
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+ * Redistribution and use in source and binary forms, with or
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+ * without modification, are permitted provided that the following
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+ * conditions are met:
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+ *
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+ * - Redistributions of source code must retain the above
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+ * copyright notice, this list of conditions and the following
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+ * disclaimer.
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+ *
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+ * - Redistributions in binary form must reproduce the above
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+ * copyright notice, this list of conditions and the following
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+ * disclaimer in the documentation and /or other materials
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+ * provided with the distribution.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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+ * SOFTWARE.
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+ */
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+#include <linux/dma-mapping.h>
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+#include <linux/crc32.h>
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+#include <linux/iommu.h>
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+#include <net/ip.h>
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+#include <net/ipv6.h>
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+#include <net/udp.h>
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+
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+#include <rdma/ib_verbs.h>
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+#include <rdma/ib_user_verbs.h>
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+#include <rdma/iw_cm.h>
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+#include <rdma/ib_umem.h>
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+#include <rdma/ib_addr.h>
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+#include <rdma/ib_cache.h>
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+
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+#include "qedr_hsi.h"
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+#include <linux/qed/qed_if.h>
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+#include <linux/qed/qed_roce_if.h>
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+#include "qedr.h"
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+#include "qedr_hsi.h"
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+#include "verbs.h"
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+#include <rdma/qedr-abi.h>
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+#include "qedr_hsi.h"
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+#include "qedr_cm.h"
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+
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+void qedr_inc_sw_gsi_cons(struct qedr_qp_hwq_info *info)
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+{
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+ info->gsi_cons = (info->gsi_cons + 1) % info->max_wr;
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+}
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+
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+void qedr_store_gsi_qp_cq(struct qedr_dev *dev, struct qedr_qp *qp,
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+ struct ib_qp_init_attr *attrs)
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+{
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+ dev->gsi_qp_created = 1;
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+ dev->gsi_sqcq = get_qedr_cq(attrs->send_cq);
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+ dev->gsi_rqcq = get_qedr_cq(attrs->recv_cq);
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+ dev->gsi_qp = qp;
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+}
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+
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+void qedr_ll2_tx_cb(void *_qdev, struct qed_roce_ll2_packet *pkt)
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+{
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+ struct qedr_dev *dev = (struct qedr_dev *)_qdev;
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+ struct qedr_cq *cq = dev->gsi_sqcq;
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+ struct qedr_qp *qp = dev->gsi_qp;
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+ unsigned long flags;
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+
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+ DP_DEBUG(dev, QEDR_MSG_GSI,
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+ "LL2 TX CB: gsi_sqcq=%p, gsi_rqcq=%p, gsi_cons=%d, ibcq_comp=%s\n",
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+ dev->gsi_sqcq, dev->gsi_rqcq, qp->sq.gsi_cons,
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+ cq->ibcq.comp_handler ? "Yes" : "No");
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+
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+ dma_free_coherent(&dev->pdev->dev, pkt->header.len, pkt->header.vaddr,
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+ pkt->header.baddr);
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+ kfree(pkt);
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+
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+ spin_lock_irqsave(&qp->q_lock, flags);
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+ qedr_inc_sw_gsi_cons(&qp->sq);
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+ spin_unlock_irqrestore(&qp->q_lock, flags);
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+
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+ if (cq->ibcq.comp_handler) {
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+ spin_lock_irqsave(&cq->comp_handler_lock, flags);
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+ (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
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+ spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
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+ }
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+}
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+
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+void qedr_ll2_rx_cb(void *_dev, struct qed_roce_ll2_packet *pkt,
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+ struct qed_roce_ll2_rx_params *params)
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+{
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+ struct qedr_dev *dev = (struct qedr_dev *)_dev;
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+ struct qedr_cq *cq = dev->gsi_rqcq;
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+ struct qedr_qp *qp = dev->gsi_qp;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&qp->q_lock, flags);
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+
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+ qp->rqe_wr_id[qp->rq.gsi_cons].rc = params->rc;
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+ qp->rqe_wr_id[qp->rq.gsi_cons].vlan_id = params->vlan_id;
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+ qp->rqe_wr_id[qp->rq.gsi_cons].sg_list[0].length = pkt->payload[0].len;
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+ ether_addr_copy(qp->rqe_wr_id[qp->rq.gsi_cons].smac, params->smac);
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+
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+ qedr_inc_sw_gsi_cons(&qp->rq);
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+
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+ spin_unlock_irqrestore(&qp->q_lock, flags);
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+
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+ if (cq->ibcq.comp_handler) {
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+ spin_lock_irqsave(&cq->comp_handler_lock, flags);
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+ (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
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+ spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
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+ }
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+}
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+
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+static void qedr_destroy_gsi_cq(struct qedr_dev *dev,
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+ struct ib_qp_init_attr *attrs)
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+{
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+ struct qed_rdma_destroy_cq_in_params iparams;
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+ struct qed_rdma_destroy_cq_out_params oparams;
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+ struct qedr_cq *cq;
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+
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+ cq = get_qedr_cq(attrs->send_cq);
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+ iparams.icid = cq->icid;
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+ dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
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+ dev->ops->common->chain_free(dev->cdev, &cq->pbl);
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+
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+ cq = get_qedr_cq(attrs->recv_cq);
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+ /* if a dedicated recv_cq was used, delete it too */
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+ if (iparams.icid != cq->icid) {
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+ iparams.icid = cq->icid;
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+ dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
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+ dev->ops->common->chain_free(dev->cdev, &cq->pbl);
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+ }
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+}
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+
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+static inline int qedr_check_gsi_qp_attrs(struct qedr_dev *dev,
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+ struct ib_qp_init_attr *attrs)
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+{
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+ if (attrs->cap.max_recv_sge > QEDR_GSI_MAX_RECV_SGE) {
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+ DP_ERR(dev,
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+ " create gsi qp: failed. max_recv_sge is larger the max %d>%d\n",
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+ attrs->cap.max_recv_sge, QEDR_GSI_MAX_RECV_SGE);
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+ return -EINVAL;
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+ }
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+
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+ if (attrs->cap.max_recv_wr > QEDR_GSI_MAX_RECV_WR) {
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+ DP_ERR(dev,
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+ " create gsi qp: failed. max_recv_wr is too large %d>%d\n",
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+ attrs->cap.max_recv_wr, QEDR_GSI_MAX_RECV_WR);
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+ return -EINVAL;
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+ }
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+
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+ if (attrs->cap.max_send_wr > QEDR_GSI_MAX_SEND_WR) {
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+ DP_ERR(dev,
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+ " create gsi qp: failed. max_send_wr is too large %d>%d\n",
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+ attrs->cap.max_send_wr, QEDR_GSI_MAX_SEND_WR);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+struct ib_qp *qedr_create_gsi_qp(struct qedr_dev *dev,
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+ struct ib_qp_init_attr *attrs,
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+ struct qedr_qp *qp)
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+{
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+ struct qed_roce_ll2_params ll2_params;
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+ int rc;
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+
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+ rc = qedr_check_gsi_qp_attrs(dev, attrs);
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+ if (rc)
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+ return ERR_PTR(rc);
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+
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+ /* configure and start LL2 */
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+ memset(&ll2_params, 0, sizeof(ll2_params));
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+ ll2_params.max_tx_buffers = attrs->cap.max_send_wr;
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+ ll2_params.max_rx_buffers = attrs->cap.max_recv_wr;
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+ ll2_params.cbs.tx_cb = qedr_ll2_tx_cb;
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+ ll2_params.cbs.rx_cb = qedr_ll2_rx_cb;
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+ ll2_params.cb_cookie = (void *)dev;
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+ ll2_params.mtu = dev->ndev->mtu;
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+ ether_addr_copy(ll2_params.mac_address, dev->ndev->dev_addr);
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+ rc = dev->ops->roce_ll2_start(dev->cdev, &ll2_params);
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+ if (rc) {
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+ DP_ERR(dev, "create gsi qp: failed on ll2 start. rc=%d\n", rc);
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+ return ERR_PTR(rc);
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+ }
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+
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+ /* create QP */
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+ qp->ibqp.qp_num = 1;
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+ qp->rq.max_wr = attrs->cap.max_recv_wr;
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+ qp->sq.max_wr = attrs->cap.max_send_wr;
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+
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+ qp->rqe_wr_id = kcalloc(qp->rq.max_wr, sizeof(*qp->rqe_wr_id),
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+ GFP_KERNEL);
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+ if (!qp->rqe_wr_id)
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+ goto err;
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+ qp->wqe_wr_id = kcalloc(qp->sq.max_wr, sizeof(*qp->wqe_wr_id),
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+ GFP_KERNEL);
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+ if (!qp->wqe_wr_id)
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+ goto err;
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+
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+ qedr_store_gsi_qp_cq(dev, qp, attrs);
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+ ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
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+
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+ /* the GSI CQ is handled by the driver so remove it from the FW */
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+ qedr_destroy_gsi_cq(dev, attrs);
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+ dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;
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+ dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;
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+
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+ DP_DEBUG(dev, QEDR_MSG_GSI, "created GSI QP %p\n", qp);
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+
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+ return &qp->ibqp;
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+
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+err:
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+ kfree(qp->rqe_wr_id);
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+
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+ rc = dev->ops->roce_ll2_stop(dev->cdev);
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+ if (rc)
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+ DP_ERR(dev, "create gsi qp: failed destroy on create\n");
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+
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+ return ERR_PTR(-ENOMEM);
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+}
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+
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+int qedr_destroy_gsi_qp(struct qedr_dev *dev)
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+{
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+ int rc;
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+
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+ rc = dev->ops->roce_ll2_stop(dev->cdev);
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+ if (rc)
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+ DP_ERR(dev, "destroy gsi qp: failed (rc=%d)\n", rc);
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+ else
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+ DP_DEBUG(dev, QEDR_MSG_GSI, "destroy gsi qp: success\n");
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+
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+ return rc;
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+}
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+
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+#define QEDR_MAX_UD_HEADER_SIZE (100)
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+#define QEDR_GSI_QPN (1)
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+static inline int qedr_gsi_build_header(struct qedr_dev *dev,
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+ struct qedr_qp *qp,
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+ struct ib_send_wr *swr,
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+ struct ib_ud_header *udh,
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+ int *roce_mode)
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+{
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+ bool has_vlan = false, has_grh_ipv6 = true;
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+ struct ib_ah_attr *ah_attr = &get_qedr_ah(ud_wr(swr)->ah)->attr;
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+ struct ib_global_route *grh = &ah_attr->grh;
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+ union ib_gid sgid;
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+ int send_size = 0;
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+ u16 vlan_id = 0;
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+ u16 ether_type;
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+ struct ib_gid_attr sgid_attr;
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+ int rc;
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+ int ip_ver = 0;
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+
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+ bool has_udp = false;
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+ int i;
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+
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+ send_size = 0;
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+ for (i = 0; i < swr->num_sge; ++i)
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+ send_size += swr->sg_list[i].length;
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+
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+ rc = ib_get_cached_gid(qp->ibqp.device, ah_attr->port_num,
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+ grh->sgid_index, &sgid, &sgid_attr);
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+ if (rc) {
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+ DP_ERR(dev,
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+ "gsi post send: failed to get cached GID (port=%d, ix=%d)\n",
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+ ah_attr->port_num, grh->sgid_index);
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+ return rc;
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+ }
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+
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+ vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
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+ if (vlan_id < VLAN_CFI_MASK)
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+ has_vlan = true;
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+ if (sgid_attr.ndev)
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+ dev_put(sgid_attr.ndev);
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+
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+ if (!memcmp(&sgid, &zgid, sizeof(sgid))) {
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+ DP_ERR(dev, "gsi post send: GID not found GID index %d\n",
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+ ah_attr->grh.sgid_index);
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+ return -ENOENT;
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+ }
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+
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+ has_udp = (sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
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+ if (!has_udp) {
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+ /* RoCE v1 */
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+ ether_type = ETH_P_ROCE;
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+ *roce_mode = ROCE_V1;
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+ } else if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) {
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+ /* RoCE v2 IPv4 */
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+ ip_ver = 4;
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+ ether_type = ETH_P_IP;
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+ has_grh_ipv6 = false;
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+ *roce_mode = ROCE_V2_IPV4;
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+ } else {
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+ /* RoCE v2 IPv6 */
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+ ip_ver = 6;
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+ ether_type = ETH_P_IPV6;
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+ *roce_mode = ROCE_V2_IPV6;
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+ }
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+
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+ rc = ib_ud_header_init(send_size, false, true, has_vlan,
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+ has_grh_ipv6, ip_ver, has_udp, 0, udh);
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+ if (rc) {
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+ DP_ERR(dev, "gsi post send: failed to init header\n");
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+ return rc;
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+ }
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+
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+ /* ENET + VLAN headers */
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+ ether_addr_copy(udh->eth.dmac_h, ah_attr->dmac);
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+ ether_addr_copy(udh->eth.smac_h, dev->ndev->dev_addr);
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+ if (has_vlan) {
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+ udh->eth.type = htons(ETH_P_8021Q);
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+ udh->vlan.tag = htons(vlan_id);
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+ udh->vlan.type = htons(ether_type);
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+ } else {
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+ udh->eth.type = htons(ether_type);
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+ }
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+
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+ /* BTH */
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+ udh->bth.solicited_event = !!(swr->send_flags & IB_SEND_SOLICITED);
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+ udh->bth.pkey = QEDR_ROCE_PKEY_DEFAULT;
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+ udh->bth.destination_qpn = htonl(ud_wr(swr)->remote_qpn);
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+ udh->bth.psn = htonl((qp->sq_psn++) & ((1 << 24) - 1));
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+ udh->bth.opcode = IB_OPCODE_UD_SEND_ONLY;
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+
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+ /* DETH */
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+ udh->deth.qkey = htonl(0x80010000);
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+ udh->deth.source_qpn = htonl(QEDR_GSI_QPN);
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+
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+ if (has_grh_ipv6) {
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+ /* GRH / IPv6 header */
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+ udh->grh.traffic_class = grh->traffic_class;
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+ udh->grh.flow_label = grh->flow_label;
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+ udh->grh.hop_limit = grh->hop_limit;
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+ udh->grh.destination_gid = grh->dgid;
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|
|
+ memcpy(&udh->grh.source_gid.raw, &sgid.raw,
|
|
|
+ sizeof(udh->grh.source_gid.raw));
|
|
|
+ } else {
|
|
|
+ /* IPv4 header */
|
|
|
+ u32 ipv4_addr;
|
|
|
+
|
|
|
+ udh->ip4.protocol = IPPROTO_UDP;
|
|
|
+ udh->ip4.tos = htonl(ah_attr->grh.flow_label);
|
|
|
+ udh->ip4.frag_off = htons(IP_DF);
|
|
|
+ udh->ip4.ttl = ah_attr->grh.hop_limit;
|
|
|
+
|
|
|
+ ipv4_addr = qedr_get_ipv4_from_gid(sgid.raw);
|
|
|
+ udh->ip4.saddr = ipv4_addr;
|
|
|
+ ipv4_addr = qedr_get_ipv4_from_gid(ah_attr->grh.dgid.raw);
|
|
|
+ udh->ip4.daddr = ipv4_addr;
|
|
|
+ /* note: checksum is calculated by the device */
|
|
|
+ }
|
|
|
+
|
|
|
+ /* UDP */
|
|
|
+ if (has_udp) {
|
|
|
+ udh->udp.sport = htons(QEDR_ROCE_V2_UDP_SPORT);
|
|
|
+ udh->udp.dport = htons(ROCE_V2_UDP_DPORT);
|
|
|
+ udh->udp.csum = 0;
|
|
|
+ /* UDP length is untouched hence is zero */
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static inline int qedr_gsi_build_packet(struct qedr_dev *dev,
|
|
|
+ struct qedr_qp *qp,
|
|
|
+ struct ib_send_wr *swr,
|
|
|
+ struct qed_roce_ll2_packet **p_packet)
|
|
|
+{
|
|
|
+ u8 ud_header_buffer[QEDR_MAX_UD_HEADER_SIZE];
|
|
|
+ struct qed_roce_ll2_packet *packet;
|
|
|
+ struct pci_dev *pdev = dev->pdev;
|
|
|
+ int roce_mode, header_size;
|
|
|
+ struct ib_ud_header udh;
|
|
|
+ int i, rc;
|
|
|
+
|
|
|
+ *p_packet = NULL;
|
|
|
+
|
|
|
+ rc = qedr_gsi_build_header(dev, qp, swr, &udh, &roce_mode);
|
|
|
+ if (rc)
|
|
|
+ return rc;
|
|
|
+
|
|
|
+ header_size = ib_ud_header_pack(&udh, &ud_header_buffer);
|
|
|
+
|
|
|
+ packet = kzalloc(sizeof(*packet), GFP_ATOMIC);
|
|
|
+ if (!packet)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ packet->header.vaddr = dma_alloc_coherent(&pdev->dev, header_size,
|
|
|
+ &packet->header.baddr,
|
|
|
+ GFP_ATOMIC);
|
|
|
+ if (!packet->header.vaddr) {
|
|
|
+ kfree(packet);
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (ether_addr_equal(udh.eth.smac_h, udh.eth.dmac_h))
|
|
|
+ packet->tx_dest = QED_ROCE_LL2_TX_DEST_NW;
|
|
|
+ else
|
|
|
+ packet->tx_dest = QED_ROCE_LL2_TX_DEST_LB;
|
|
|
+
|
|
|
+ packet->roce_mode = roce_mode;
|
|
|
+ memcpy(packet->header.vaddr, ud_header_buffer, header_size);
|
|
|
+ packet->header.len = header_size;
|
|
|
+ packet->n_seg = swr->num_sge;
|
|
|
+ for (i = 0; i < packet->n_seg; i++) {
|
|
|
+ packet->payload[i].baddr = swr->sg_list[i].addr;
|
|
|
+ packet->payload[i].len = swr->sg_list[i].length;
|
|
|
+ }
|
|
|
+
|
|
|
+ *p_packet = packet;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int qedr_gsi_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
|
|
|
+ struct ib_send_wr **bad_wr)
|
|
|
+{
|
|
|
+ struct qed_roce_ll2_packet *pkt = NULL;
|
|
|
+ struct qedr_qp *qp = get_qedr_qp(ibqp);
|
|
|
+ struct qed_roce_ll2_tx_params params;
|
|
|
+ struct qedr_dev *dev = qp->dev;
|
|
|
+ unsigned long flags;
|
|
|
+ int rc;
|
|
|
+
|
|
|
+ if (qp->state != QED_ROCE_QP_STATE_RTS) {
|
|
|
+ *bad_wr = wr;
|
|
|
+ DP_ERR(dev,
|
|
|
+ "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTS\n",
|
|
|
+ qp->state);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (wr->num_sge > RDMA_MAX_SGE_PER_SQ_WQE) {
|
|
|
+ DP_ERR(dev, "gsi post send: num_sge is too large (%d>%d)\n",
|
|
|
+ wr->num_sge, RDMA_MAX_SGE_PER_SQ_WQE);
|
|
|
+ rc = -EINVAL;
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (wr->opcode != IB_WR_SEND) {
|
|
|
+ DP_ERR(dev,
|
|
|
+ "gsi post send: failed due to unsupported opcode %d\n",
|
|
|
+ wr->opcode);
|
|
|
+ rc = -EINVAL;
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ memset(¶ms, 0, sizeof(params));
|
|
|
+
|
|
|
+ spin_lock_irqsave(&qp->q_lock, flags);
|
|
|
+
|
|
|
+ rc = qedr_gsi_build_packet(dev, qp, wr, &pkt);
|
|
|
+ if (rc) {
|
|
|
+ spin_unlock_irqrestore(&qp->q_lock, flags);
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ rc = dev->ops->roce_ll2_tx(dev->cdev, pkt, ¶ms);
|
|
|
+ if (!rc) {
|
|
|
+ qp->wqe_wr_id[qp->sq.prod].wr_id = wr->wr_id;
|
|
|
+ qedr_inc_sw_prod(&qp->sq);
|
|
|
+ DP_DEBUG(qp->dev, QEDR_MSG_GSI,
|
|
|
+ "gsi post send: opcode=%d, in_irq=%ld, irqs_disabled=%d, wr_id=%llx\n",
|
|
|
+ wr->opcode, in_irq(), irqs_disabled(), wr->wr_id);
|
|
|
+ } else {
|
|
|
+ if (rc == QED_ROCE_TX_HEAD_FAILURE) {
|
|
|
+ /* TX failed while posting header - release resources */
|
|
|
+ dma_free_coherent(&dev->pdev->dev, pkt->header.len,
|
|
|
+ pkt->header.vaddr, pkt->header.baddr);
|
|
|
+ kfree(pkt);
|
|
|
+ } else if (rc == QED_ROCE_TX_FRAG_FAILURE) {
|
|
|
+ /* NTD since TX failed while posting a fragment. We will
|
|
|
+ * release the resources on TX callback
|
|
|
+ */
|
|
|
+ }
|
|
|
+
|
|
|
+ DP_ERR(dev, "gsi post send: failed to transmit (rc=%d)\n", rc);
|
|
|
+ rc = -EAGAIN;
|
|
|
+ *bad_wr = wr;
|
|
|
+ }
|
|
|
+
|
|
|
+ spin_unlock_irqrestore(&qp->q_lock, flags);
|
|
|
+
|
|
|
+ if (wr->next) {
|
|
|
+ DP_ERR(dev,
|
|
|
+ "gsi post send: failed second WR. Only one WR may be passed at a time\n");
|
|
|
+ *bad_wr = wr->next;
|
|
|
+ rc = -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ return rc;
|
|
|
+
|
|
|
+err:
|
|
|
+ *bad_wr = wr;
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
+int qedr_gsi_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
|
|
|
+ struct ib_recv_wr **bad_wr)
|
|
|
+{
|
|
|
+ struct qedr_dev *dev = get_qedr_dev(ibqp->device);
|
|
|
+ struct qedr_qp *qp = get_qedr_qp(ibqp);
|
|
|
+ struct qed_roce_ll2_buffer buf;
|
|
|
+ unsigned long flags;
|
|
|
+ int status = 0;
|
|
|
+ int rc;
|
|
|
+
|
|
|
+ if ((qp->state != QED_ROCE_QP_STATE_RTR) &&
|
|
|
+ (qp->state != QED_ROCE_QP_STATE_RTS)) {
|
|
|
+ *bad_wr = wr;
|
|
|
+ DP_ERR(dev,
|
|
|
+ "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTR/S\n",
|
|
|
+ qp->state);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ memset(&buf, 0, sizeof(buf));
|
|
|
+
|
|
|
+ spin_lock_irqsave(&qp->q_lock, flags);
|
|
|
+
|
|
|
+ while (wr) {
|
|
|
+ if (wr->num_sge > QEDR_GSI_MAX_RECV_SGE) {
|
|
|
+ DP_ERR(dev,
|
|
|
+ "gsi post recv: failed to post rx buffer. too many sges %d>%d\n",
|
|
|
+ wr->num_sge, QEDR_GSI_MAX_RECV_SGE);
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ buf.baddr = wr->sg_list[0].addr;
|
|
|
+ buf.len = wr->sg_list[0].length;
|
|
|
+
|
|
|
+ rc = dev->ops->roce_ll2_post_rx_buffer(dev->cdev, &buf, 0, 1);
|
|
|
+ if (rc) {
|
|
|
+ DP_ERR(dev,
|
|
|
+ "gsi post recv: failed to post rx buffer (rc=%d)\n",
|
|
|
+ rc);
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ memset(&qp->rqe_wr_id[qp->rq.prod], 0,
|
|
|
+ sizeof(qp->rqe_wr_id[qp->rq.prod]));
|
|
|
+ qp->rqe_wr_id[qp->rq.prod].sg_list[0] = wr->sg_list[0];
|
|
|
+ qp->rqe_wr_id[qp->rq.prod].wr_id = wr->wr_id;
|
|
|
+
|
|
|
+ qedr_inc_sw_prod(&qp->rq);
|
|
|
+
|
|
|
+ wr = wr->next;
|
|
|
+ }
|
|
|
+
|
|
|
+ spin_unlock_irqrestore(&qp->q_lock, flags);
|
|
|
+
|
|
|
+ return status;
|
|
|
+err:
|
|
|
+ spin_unlock_irqrestore(&qp->q_lock, flags);
|
|
|
+ *bad_wr = wr;
|
|
|
+ return -ENOMEM;
|
|
|
+}
|
|
|
+
|
|
|
+int qedr_gsi_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
|
|
|
+{
|
|
|
+ struct qedr_dev *dev = get_qedr_dev(ibcq->device);
|
|
|
+ struct qedr_cq *cq = get_qedr_cq(ibcq);
|
|
|
+ struct qedr_qp *qp = dev->gsi_qp;
|
|
|
+ unsigned long flags;
|
|
|
+ int i = 0;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&cq->cq_lock, flags);
|
|
|
+
|
|
|
+ while (i < num_entries && qp->rq.cons != qp->rq.gsi_cons) {
|
|
|
+ memset(&wc[i], 0, sizeof(*wc));
|
|
|
+
|
|
|
+ wc[i].qp = &qp->ibqp;
|
|
|
+ wc[i].wr_id = qp->rqe_wr_id[qp->rq.cons].wr_id;
|
|
|
+ wc[i].opcode = IB_WC_RECV;
|
|
|
+ wc[i].pkey_index = 0;
|
|
|
+ wc[i].status = (qp->rqe_wr_id[qp->rq.cons].rc) ?
|
|
|
+ IB_WC_GENERAL_ERR : IB_WC_SUCCESS;
|
|
|
+ /* 0 - currently only one recv sg is supported */
|
|
|
+ wc[i].byte_len = qp->rqe_wr_id[qp->rq.cons].sg_list[0].length;
|
|
|
+ wc[i].wc_flags |= IB_WC_GRH | IB_WC_IP_CSUM_OK;
|
|
|
+ ether_addr_copy(wc[i].smac, qp->rqe_wr_id[qp->rq.cons].smac);
|
|
|
+ wc[i].wc_flags |= IB_WC_WITH_SMAC;
|
|
|
+ if (qp->rqe_wr_id[qp->rq.cons].vlan_id) {
|
|
|
+ wc[i].wc_flags |= IB_WC_WITH_VLAN;
|
|
|
+ wc[i].vlan_id = qp->rqe_wr_id[qp->rq.cons].vlan_id;
|
|
|
+ }
|
|
|
+
|
|
|
+ qedr_inc_sw_cons(&qp->rq);
|
|
|
+ i++;
|
|
|
+ }
|
|
|
+
|
|
|
+ while (i < num_entries && qp->sq.cons != qp->sq.gsi_cons) {
|
|
|
+ memset(&wc[i], 0, sizeof(*wc));
|
|
|
+
|
|
|
+ wc[i].qp = &qp->ibqp;
|
|
|
+ wc[i].wr_id = qp->wqe_wr_id[qp->sq.cons].wr_id;
|
|
|
+ wc[i].opcode = IB_WC_SEND;
|
|
|
+ wc[i].status = IB_WC_SUCCESS;
|
|
|
+
|
|
|
+ qedr_inc_sw_cons(&qp->sq);
|
|
|
+ i++;
|
|
|
+ }
|
|
|
+
|
|
|
+ spin_unlock_irqrestore(&cq->cq_lock, flags);
|
|
|
+
|
|
|
+ DP_DEBUG(dev, QEDR_MSG_GSI,
|
|
|
+ "gsi poll_cq: requested entries=%d, actual=%d, qp->rq.cons=%d, qp->rq.gsi_cons=%x, qp->sq.cons=%d, qp->sq.gsi_cons=%d, qp_num=%d\n",
|
|
|
+ num_entries, i, qp->rq.cons, qp->rq.gsi_cons, qp->sq.cons,
|
|
|
+ qp->sq.gsi_cons, qp->ibqp.qp_num);
|
|
|
+
|
|
|
+ return i;
|
|
|
+}
|
Ram Amrani