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@@ -161,7 +161,6 @@
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#define SDHCI_CTRL_UHS_SDR50 0x0002
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#define SDHCI_CTRL_UHS_SDR50 0x0002
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#define SDHCI_CTRL_UHS_SDR104 0x0003
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#define SDHCI_CTRL_UHS_SDR104 0x0003
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#define SDHCI_CTRL_UHS_DDR50 0x0004
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#define SDHCI_CTRL_UHS_DDR50 0x0004
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-#define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */
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#define SDHCI_CTRL_VDD_180 0x0008
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#define SDHCI_CTRL_VDD_180 0x0008
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#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
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#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
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#define SDHCI_CTRL_DRV_TYPE_B 0x0000
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#define SDHCI_CTRL_DRV_TYPE_B 0x0000
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