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@@ -49,10 +49,23 @@
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#define I40E_QUEUE_END_OF_LIST 0x7FF
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-#define I40E_ITR_NONE 3
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-#define I40E_RX_ITR 0
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-#define I40E_TX_ITR 1
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-#define I40E_PE_ITR 2
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+/* this enum matches hardware bits and is meant to be used by DYN_CTLN
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+ * registers and QINT registers or more generally anywhere in the manual
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+ * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
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+ * register but instead is a special value meaning "don't update" ITR0/1/2.
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+ */
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+enum i40e_dyn_idx_t {
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+ I40E_IDX_ITR0 = 0,
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+ I40E_IDX_ITR1 = 1,
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+ I40E_IDX_ITR2 = 2,
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+ I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
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+};
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+
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+/* these are indexes into ITRN registers */
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+#define I40E_RX_ITR I40E_IDX_ITR0
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+#define I40E_TX_ITR I40E_IDX_ITR1
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+#define I40E_PE_ITR I40E_IDX_ITR2
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+
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/* Supported Rx Buffer Sizes */
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#define I40E_RXBUFFER_512 512 /* Used for packet split */
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#define I40E_RXBUFFER_2048 2048
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