950-sparc-leon.patch 8.0 KB

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  1. diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/leon.md gcc-4.4.2/gcc/config/sparc/leon.md
  2. --- gcc-4.4.2.ori/gcc/config/sparc/leon.md 1970-01-01 01:00:00.000000000 +0100
  3. +++ gcc-4.4.2/gcc/config/sparc/leon.md 2010-10-19 11:56:58.000000000 +0200
  4. @@ -0,0 +1,56 @@
  5. +;; Scheduling description for Leon.
  6. +;; Copyright (C) 2010 Free Software Foundation, Inc.
  7. +;;
  8. +;; This file is part of GCC.
  9. +;;
  10. +;; GCC is free software; you can redistribute it and/or modify
  11. +;; it under the terms of the GNU General Public License as published by
  12. +;; the Free Software Foundation; either version 3, or (at your option)
  13. +;; any later version.
  14. +;;
  15. +;; GCC is distributed in the hope that it will be useful,
  16. +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. +;; GNU General Public License for more details.
  19. +;;
  20. +;; You should have received a copy of the GNU General Public License
  21. +;; along with GCC; see the file COPYING3. If not see
  22. +;; <http://www.gnu.org/licenses/>.
  23. +
  24. +
  25. +(define_automaton "leon")
  26. +
  27. +(define_cpu_unit "leon_memory, leon_fpalu" "leon")
  28. +(define_cpu_unit "leon_fpmds" "leon")
  29. +(define_cpu_unit "write_buf" "leon")
  30. +
  31. +(define_insn_reservation "leon_load" 1
  32. + (and (eq_attr "cpu" "leon")
  33. + (eq_attr "type" "load,sload,fpload"))
  34. + "leon_memory")
  35. +
  36. +(define_insn_reservation "leon_store" 1
  37. + (and (eq_attr "cpu" "leon")
  38. + (eq_attr "type" "store,fpstore"))
  39. + "leon_memory+write_buf")
  40. +
  41. +(define_insn_reservation "leon_fp_alu" 1
  42. + (and (eq_attr "cpu" "leon")
  43. + (eq_attr "type" "fp,fpmove"))
  44. + "leon_fpalu, nothing")
  45. +
  46. +(define_insn_reservation "leon_fp_mult" 1
  47. + (and (eq_attr "cpu" "leon")
  48. + (eq_attr "type" "fpmul"))
  49. + "leon_fpmds, nothing")
  50. +
  51. +(define_insn_reservation "leon_fp_div" 16
  52. + (and (eq_attr "cpu" "leon")
  53. + (eq_attr "type" "fpdivs,fpdivd"))
  54. + "leon_fpmds, nothing*15")
  55. +
  56. +(define_insn_reservation "leon_fp_sqrt" 23
  57. + (and (eq_attr "cpu" "leon")
  58. + (eq_attr "type" "fpsqrts,fpsqrtd"))
  59. + "leon_fpmds, nothing*21")
  60. +
  61. diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/sparc.c gcc-4.4.2/gcc/config/sparc/sparc.c
  62. --- gcc-4.4.2.ori/gcc/config/sparc/sparc.c 2010-10-19 11:55:17.000000000 +0200
  63. +++ gcc-4.4.2/gcc/config/sparc/sparc.c 2010-10-19 11:56:58.000000000 +0200
  64. @@ -246,6 +246,30 @@
  65. 0, /* shift penalty */
  66. };
  67. +static const
  68. +struct processor_costs leon_costs = {
  69. + COSTS_N_INSNS (1), /* int load */
  70. + COSTS_N_INSNS (1), /* int signed load */
  71. + COSTS_N_INSNS (1), /* int zeroed load */
  72. + COSTS_N_INSNS (1), /* float load */
  73. + COSTS_N_INSNS (1), /* fmov, fneg, fabs */
  74. + COSTS_N_INSNS (1), /* fadd, fsub */
  75. + COSTS_N_INSNS (1), /* fcmp */
  76. + COSTS_N_INSNS (1), /* fmov, fmovr */
  77. + COSTS_N_INSNS (1), /* fmul */
  78. + COSTS_N_INSNS (15), /* fdivs */
  79. + COSTS_N_INSNS (15), /* fdivd */
  80. + COSTS_N_INSNS (23), /* fsqrts */
  81. + COSTS_N_INSNS (23), /* fsqrtd */
  82. + COSTS_N_INSNS (5), /* imul */
  83. + COSTS_N_INSNS (5), /* imulX */
  84. + 0, /* imul bit factor */
  85. + COSTS_N_INSNS (5), /* idiv */
  86. + COSTS_N_INSNS (5), /* idivX */
  87. + COSTS_N_INSNS (1), /* movcc/movr */
  88. + 0, /* shift penalty */
  89. +};
  90. +
  91. const struct processor_costs *sparc_costs = &cypress_costs;
  92. #ifdef HAVE_AS_RELAX_OPTION
  93. @@ -651,6 +675,10 @@
  94. { TARGET_CPU_ultrasparc3, "ultrasparc3" },
  95. { TARGET_CPU_niagara, "niagara" },
  96. { TARGET_CPU_niagara2, "niagara2" },
  97. + { TARGET_CPU_sparchfleon, "sparchfleon" },
  98. + { TARGET_CPU_sparchfleonv8, "sparchfleonv8" },
  99. + { TARGET_CPU_sparcsfleon, "sparcsfleon" },
  100. + { TARGET_CPU_sparcsfleonv8, "sparcsfleonv8" },
  101. { 0, 0 }
  102. };
  103. const struct cpu_default *def;
  104. @@ -689,6 +717,11 @@
  105. /* UltraSPARC T1 */
  106. { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
  107. { "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9},
  108. + /* SPARC-LEON */
  109. + { "sparchfleon", PROCESSOR_LEON, MASK_ISA, MASK_FPU },
  110. + { "sparchfleonv8", PROCESSOR_LEON, MASK_ISA & ~(MASK_V8), MASK_V8|MASK_FPU },
  111. + { "sparcsfleon", PROCESSOR_LEON, MASK_ISA | MASK_FPU, 0 },
  112. + { "sparcsfleonv8", PROCESSOR_LEON, (MASK_ISA | MASK_FPU) & ~(MASK_V8), MASK_V8 },
  113. { 0, 0, 0, 0 }
  114. };
  115. const struct cpu_table *cpu;
  116. @@ -855,6 +888,9 @@
  117. case PROCESSOR_NIAGARA2:
  118. sparc_costs = &niagara2_costs;
  119. break;
  120. + case PROCESSOR_LEON:
  121. + sparc_costs = &leon_costs;
  122. + break;
  123. };
  124. #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
  125. diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/sparc.h gcc-4.4.2/gcc/config/sparc/sparc.h
  126. --- gcc-4.4.2.ori/gcc/config/sparc/sparc.h 2010-10-19 11:55:17.000000000 +0200
  127. +++ gcc-4.4.2/gcc/config/sparc/sparc.h 2010-10-19 11:56:58.000000000 +0200
  128. @@ -243,6 +243,10 @@
  129. #define TARGET_CPU_ultrasparc3 9
  130. #define TARGET_CPU_niagara 10
  131. #define TARGET_CPU_niagara2 11
  132. +#define TARGET_CPU_sparchfleon 12
  133. +#define TARGET_CPU_sparchfleonv8 13
  134. +#define TARGET_CPU_sparcsfleon 14
  135. +#define TARGET_CPU_sparcsfleonv8 15
  136. #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
  137. || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
  138. @@ -299,6 +303,26 @@
  139. #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
  140. #endif
  141. +#if TARGET_CPU_DEFAULT == TARGET_CPU_sparchfleon
  142. +#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon"
  143. +#define ASM_CPU32_DEFAULT_SPEC ""
  144. +#endif
  145. +
  146. +#if TARGET_CPU_DEFAULT == TARGET_CPU_sparcsfleon
  147. +#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon -D_SOFT_FLOAT"
  148. +#define ASM_CPU32_DEFAULT_SPEC ""
  149. +#endif
  150. +
  151. +#if TARGET_CPU_DEFAULT == TARGET_CPU_sparchfleonv8
  152. +#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon -D__sparc_v8__ "
  153. +#define ASM_CPU32_DEFAULT_SPEC ""
  154. +#endif
  155. +
  156. +#if TARGET_CPU_DEFAULT == TARGET_CPU_sparcsfleonv8
  157. +#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon -D__sparc_v8__ -D_SOFT_FLOAT"
  158. +#define ASM_CPU32_DEFAULT_SPEC ""
  159. +#endif
  160. +
  161. #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
  162. #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
  163. #define ASM_CPU32_DEFAULT_SPEC ""
  164. @@ -369,6 +393,10 @@
  165. %{mcpu=ultrasparc3:-D__sparc_v9__} \
  166. %{mcpu=niagara:-D__sparc_v9__} \
  167. %{mcpu=niagara2:-D__sparc_v9__} \
  168. +%{mcpu=sparchfleon:-Dsparcleon} \
  169. +%{mcpu=sparchfleonv8:-Dsparcleon -D__sparc_v8__} \
  170. +%{mcpu=sparcsfleon:-Dsparcleon -D_SOFT_FLOAT} \
  171. +%{mcpu=sparcsfleonv8:-Dsparcleon -D_SOFT_FLOAT -D__sparc_v8__} \
  172. %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
  173. "
  174. #define CPP_ARCH32_SPEC ""
  175. @@ -533,6 +561,7 @@
  176. PROCESSOR_V7,
  177. PROCESSOR_CYPRESS,
  178. PROCESSOR_V8,
  179. + PROCESSOR_LEON,
  180. PROCESSOR_SUPERSPARC,
  181. PROCESSOR_SPARCLITE,
  182. PROCESSOR_F930,
  183. diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/sparc.md gcc-4.4.2/gcc/config/sparc/sparc.md
  184. --- gcc-4.4.2.ori/gcc/config/sparc/sparc.md 2010-10-19 11:55:17.000000000 +0200
  185. +++ gcc-4.4.2/gcc/config/sparc/sparc.md 2010-10-19 11:56:58.000000000 +0200
  186. @@ -89,6 +89,7 @@
  187. "v7,
  188. cypress,
  189. v8,
  190. + leon,
  191. supersparc,
  192. sparclite,f930,f934,
  193. hypersparc,sparclite86x,
  194. @@ -320,6 +321,7 @@
  195. (include "ultra3.md")
  196. (include "niagara.md")
  197. (include "niagara2.md")
  198. +(include "leon.md")
  199. ;; Operand and operator predicates and constraints
  200. diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/t-leon gcc-4.4.2/gcc/config/sparc/t-leon
  201. --- gcc-4.4.2.ori/gcc/config/sparc/t-leon 1970-01-01 01:00:00.000000000 +0100
  202. +++ gcc-4.4.2/gcc/config/sparc/t-leon 2010-10-19 11:56:58.000000000 +0200
  203. @@ -0,0 +1,16 @@
  204. +# configuration file for LEON cpu
  205. +
  206. +LIB1ASMSRC = sparc/lb1spc.asm
  207. +LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3
  208. +
  209. +# We want fine grained libraries, so use the new code to build the
  210. +# floating point emulation libraries.
  211. +FPBIT = fp-bit.c
  212. +DPBIT = dp-bit.c
  213. +
  214. +dp-bit.c: $(srcdir)/config/fp-bit.c
  215. + cat $(srcdir)/config/fp-bit.c > dp-bit.c
  216. +
  217. +fp-bit.c: $(srcdir)/config/fp-bit.c
  218. + echo '#define FLOAT' > fp-bit.c
  219. + cat $(srcdir)/config/fp-bit.c >> fp-bit.c
  220. diff -Naurb gcc-4.4.2.ori/gcc/config.gcc gcc-4.4.2/gcc/config.gcc
  221. --- gcc-4.4.2.ori/gcc/config.gcc 2010-10-19 11:55:17.000000000 +0200
  222. +++ gcc-4.4.2/gcc/config.gcc 2010-10-19 11:56:11.000000000 +0200
  223. @@ -2978,6 +2978,9 @@
  224. | v9 | ultrasparc | ultrasparc3 | niagara | niagara2)
  225. # OK
  226. ;;
  227. + sparchfleon | sparcsfleon | sparchfleonv8 | sparcsfleonv8 | leon)
  228. + tmake_file="${tmake_file} sparc/t-leon"
  229. + ;;
  230. *)
  231. echo "Unknown cpu used in --with-$which=$val" 1>&2
  232. exit 1