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Config.in 11 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. config BR2_ARCH_HAS_FDPIC_SUPPORT
  13. bool
  14. choice
  15. prompt "Target Architecture"
  16. default BR2_i386
  17. help
  18. Select the target architecture family to build for.
  19. config BR2_arcle
  20. bool "ARC (little endian)"
  21. select BR2_ARCH_HAS_MMU_MANDATORY
  22. help
  23. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  24. that can be used from deeply embedded to high performance host
  25. applications. Little endian.
  26. config BR2_arceb
  27. bool "ARC (big endian)"
  28. select BR2_ARCH_HAS_MMU_MANDATORY
  29. help
  30. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  31. that can be used from deeply embedded to high performance host
  32. applications. Big endian.
  33. config BR2_arm
  34. bool "ARM (little endian)"
  35. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  36. help
  37. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  38. set architecture (ISA) developed by ARM Holdings. Little endian.
  39. http://www.arm.com/
  40. http://en.wikipedia.org/wiki/ARM
  41. config BR2_armeb
  42. bool "ARM (big endian)"
  43. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  44. help
  45. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  46. set architecture (ISA) developed by ARM Holdings. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. select BR2_ARCH_HAS_MMU_MANDATORY
  53. help
  54. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  55. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  56. http://en.wikipedia.org/wiki/ARM
  57. config BR2_aarch64_be
  58. bool "AArch64 (big endian)"
  59. select BR2_ARCH_IS_64
  60. select BR2_ARCH_HAS_MMU_MANDATORY
  61. help
  62. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  63. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  64. http://en.wikipedia.org/wiki/ARM
  65. config BR2_bfin
  66. bool "Blackfin"
  67. select BR2_ARCH_HAS_FDPIC_SUPPORT
  68. help
  69. The Blackfin is a family of 16 or 32-bit microprocessors developed,
  70. manufactured and marketed by Analog Devices.
  71. http://www.analog.com/
  72. http://en.wikipedia.org/wiki/Blackfin
  73. config BR2_i386
  74. bool "i386"
  75. select BR2_ARCH_HAS_MMU_MANDATORY
  76. help
  77. Intel i386 architecture compatible microprocessor
  78. http://en.wikipedia.org/wiki/I386
  79. config BR2_m68k
  80. bool "m68k"
  81. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  82. help
  83. Motorola 68000 family microprocessor
  84. http://en.wikipedia.org/wiki/M68k
  85. config BR2_microblazeel
  86. bool "Microblaze AXI (little endian)"
  87. select BR2_ARCH_HAS_MMU_MANDATORY
  88. help
  89. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
  90. based architecture (little endian)
  91. http://www.xilinx.com
  92. http://en.wikipedia.org/wiki/Microblaze
  93. config BR2_microblazebe
  94. bool "Microblaze non-AXI (big endian)"
  95. select BR2_ARCH_HAS_MMU_MANDATORY
  96. help
  97. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
  98. based architecture (non-AXI, big endian)
  99. http://www.xilinx.com
  100. http://en.wikipedia.org/wiki/Microblaze
  101. config BR2_mips
  102. bool "MIPS (big endian)"
  103. select BR2_ARCH_HAS_MMU_MANDATORY
  104. help
  105. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  106. http://www.mips.com/
  107. http://en.wikipedia.org/wiki/MIPS_Technologies
  108. config BR2_mipsel
  109. bool "MIPS (little endian)"
  110. select BR2_ARCH_HAS_MMU_MANDATORY
  111. help
  112. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  113. http://www.mips.com/
  114. http://en.wikipedia.org/wiki/MIPS_Technologies
  115. config BR2_mips64
  116. bool "MIPS64 (big endian)"
  117. select BR2_ARCH_IS_64
  118. select BR2_ARCH_HAS_MMU_MANDATORY
  119. help
  120. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  121. http://www.mips.com/
  122. http://en.wikipedia.org/wiki/MIPS_Technologies
  123. config BR2_mips64el
  124. bool "MIPS64 (little endian)"
  125. select BR2_ARCH_IS_64
  126. select BR2_ARCH_HAS_MMU_MANDATORY
  127. help
  128. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  129. http://www.mips.com/
  130. http://en.wikipedia.org/wiki/MIPS_Technologies
  131. config BR2_nios2
  132. bool "Nios II"
  133. select BR2_ARCH_HAS_MMU_MANDATORY
  134. help
  135. Nios II is a soft core processor from Altera Corporation.
  136. http://www.altera.com/
  137. http://en.wikipedia.org/wiki/Nios_II
  138. config BR2_powerpc
  139. bool "PowerPC"
  140. select BR2_ARCH_HAS_MMU_MANDATORY
  141. help
  142. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  143. Big endian.
  144. http://www.power.org/
  145. http://en.wikipedia.org/wiki/Powerpc
  146. config BR2_powerpc64
  147. bool "PowerPC64 (big endian)"
  148. select BR2_ARCH_IS_64
  149. select BR2_ARCH_HAS_MMU_MANDATORY
  150. help
  151. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  152. Big endian.
  153. http://www.power.org/
  154. http://en.wikipedia.org/wiki/Powerpc
  155. config BR2_powerpc64le
  156. bool "PowerPC64 (little endian)"
  157. select BR2_ARCH_IS_64
  158. select BR2_ARCH_HAS_MMU_MANDATORY
  159. help
  160. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  161. Little endian.
  162. http://www.power.org/
  163. http://en.wikipedia.org/wiki/Powerpc
  164. config BR2_sh
  165. bool "SuperH"
  166. select BR2_ARCH_HAS_MMU_OPTIONAL
  167. help
  168. SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
  169. instruction set architecture (ISA) developed by Hitachi.
  170. http://www.hitachi.com/
  171. http://en.wikipedia.org/wiki/SuperH
  172. config BR2_sh64
  173. bool "SuperH64"
  174. depends on BR2_DEPRECATED_SINCE_2015_05
  175. select BR2_ARCH_HAS_MMU_MANDATORY
  176. help
  177. SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
  178. instruction set architecture (ISA) developed by Hitachi.
  179. http://www.hitachi.com/
  180. http://en.wikipedia.org/wiki/SuperH
  181. config BR2_sparc
  182. bool "SPARC"
  183. select BR2_ARCH_HAS_MMU_MANDATORY
  184. help
  185. SPARC (from Scalable Processor Architecture) is a RISC instruction
  186. set architecture (ISA) developed by Sun Microsystems.
  187. http://www.oracle.com/sun
  188. http://en.wikipedia.org/wiki/Sparc
  189. config BR2_sparc64
  190. bool "SPARC64"
  191. select BR2_ARCH_IS_64
  192. select BR2_ARCH_HAS_MMU_MANDATORY
  193. help
  194. SPARC (from Scalable Processor Architecture) is a RISC instruction
  195. set architecture (ISA) developed by Sun Microsystems.
  196. http://www.oracle.com/sun
  197. http://en.wikipedia.org/wiki/Sparc
  198. config BR2_x86_64
  199. bool "x86_64"
  200. select BR2_ARCH_IS_64
  201. select BR2_ARCH_HAS_MMU_MANDATORY
  202. help
  203. x86-64 is an extension of the x86 instruction set (Intel i386
  204. architecture compatible microprocessor).
  205. http://en.wikipedia.org/wiki/X86_64
  206. config BR2_xtensa
  207. bool "Xtensa"
  208. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  209. help
  210. Xtensa is a Tensilica processor IP architecture.
  211. http://en.wikipedia.org/wiki/Xtensa
  212. http://www.tensilica.com/
  213. endchoice
  214. # The following string values are defined by the individual
  215. # Config.in.$ARCH files
  216. config BR2_ARCH
  217. string
  218. config BR2_ENDIAN
  219. string
  220. config BR2_GCC_TARGET_ARCH
  221. string
  222. config BR2_GCC_TARGET_ABI
  223. string
  224. config BR2_GCC_TARGET_CPU
  225. string
  226. config BR2_GCC_TARGET_CPU_REVISION
  227. string
  228. # The value of this option will be passed as --with-fpu=<value> when
  229. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  230. # wrapper (external toolchain)
  231. config BR2_GCC_TARGET_FPU
  232. string
  233. # The value of this option will be passed as --with-float=<value> when
  234. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  235. # wrapper (external toolchain)
  236. config BR2_GCC_TARGET_FLOAT_ABI
  237. string
  238. # The value of this option will be passed as --with-mode=<value> when
  239. # building gcc (internal backend) or -m<value> in the toolchain
  240. # wrapper (external toolchain)
  241. config BR2_GCC_TARGET_MODE
  242. string
  243. # Must be selected by binary formats that support shared libraries.
  244. config BR2_BINFMT_SUPPORTS_SHARED
  245. bool
  246. # Set up target binary format
  247. choice
  248. prompt "Target Binary Format"
  249. default BR2_BINFMT_ELF if BR2_USE_MMU
  250. default BR2_BINFMT_FDPIC if BR2_ARCH_HAS_FDPIC_SUPPORT
  251. default BR2_BINFMT_FLAT
  252. config BR2_BINFMT_ELF
  253. bool "ELF"
  254. depends on BR2_USE_MMU
  255. select BR2_BINFMT_SUPPORTS_SHARED
  256. help
  257. ELF (Executable and Linkable Format) is a format for libraries and
  258. executables used across different architectures and operating
  259. systems.
  260. config BR2_BINFMT_FDPIC
  261. bool "FDPIC"
  262. depends on BR2_ARCH_HAS_FDPIC_SUPPORT
  263. select BR2_BINFMT_SUPPORTS_SHARED
  264. help
  265. ELF FDPIC binaries are based on ELF, but allow the individual load
  266. segments of a binary to be located in memory independently of each
  267. other. This makes this format ideal for use in environments where no
  268. MMU is available.
  269. config BR2_BINFMT_FLAT
  270. bool "FLAT"
  271. depends on !BR2_USE_MMU
  272. help
  273. FLAT binary is a relatively simple and lightweight executable format
  274. based on the original a.out format. It is widely used in environment
  275. where no MMU is available.
  276. endchoice
  277. # Set up flat binary type
  278. choice
  279. prompt "FLAT Binary type"
  280. depends on BR2_BINFMT_FLAT
  281. default BR2_BINFMT_FLAT_ONE
  282. config BR2_BINFMT_FLAT_ONE
  283. bool "One memory region"
  284. depends on !BR2_m68k
  285. help
  286. All segments are linked into one memory region.
  287. config BR2_BINFMT_FLAT_SEP_DATA
  288. bool "Separate data and code region"
  289. depends on BR2_m68k || BR2_bfin
  290. help
  291. Allow for the data and text segments to be separated and placed in
  292. different regions of memory.
  293. config BR2_BINFMT_FLAT_SHARED
  294. bool "Shared binary"
  295. depends on BR2_m68k || BR2_bfin
  296. # Even though this really generates shared binaries, there is no libdl
  297. # and dlopen() cannot be used. So packages that require shared
  298. # libraries cannot be built. Therefore, we don't select
  299. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  300. # Although this adds -static to the compilation, that's not a problem
  301. # because the -mid-shared-library option overrides it.
  302. help
  303. Allow to load and link indiviual FLAT binaries at run time.
  304. endchoice
  305. if BR2_arcle || BR2_arceb
  306. source "arch/Config.in.arc"
  307. endif
  308. if BR2_arm || BR2_armeb
  309. source "arch/Config.in.arm"
  310. endif
  311. if BR2_aarch64 || BR2_aarch64_be
  312. source "arch/Config.in.aarch64"
  313. endif
  314. if BR2_bfin
  315. source "arch/Config.in.bfin"
  316. endif
  317. if BR2_m68k
  318. source "arch/Config.in.m68k"
  319. endif
  320. if BR2_microblazeel || BR2_microblazebe
  321. source "arch/Config.in.microblaze"
  322. endif
  323. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  324. source "arch/Config.in.mips"
  325. endif
  326. if BR2_nios2
  327. source "arch/Config.in.nios2"
  328. endif
  329. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  330. source "arch/Config.in.powerpc"
  331. endif
  332. if BR2_sh || BR2_sh64
  333. source "arch/Config.in.sh"
  334. endif
  335. if BR2_sparc || BR2_sparc64
  336. source "arch/Config.in.sparc"
  337. endif
  338. if BR2_i386 || BR2_x86_64
  339. source "arch/Config.in.x86"
  340. endif
  341. if BR2_xtensa
  342. source "arch/Config.in.xtensa"
  343. endif
  344. endmenu # Target options