0002-replace-uart2-by-uart5.patch 2.6 KB

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  1. From: Fabio Estevam <fabio.estevam@freescale.com>
  2. Date: Fri, 29 May 2015 16:19:39 -0300
  3. Subject: [PATCH] ARM: dts: imx6sl-warp: Add changes for rev1.12
  4. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
  5. ---
  6. arch/arm/boot/dts/imx6sl-warp.dts | 32 +++++++++++++++++++-------------
  7. 1 file changed, 19 insertions(+), 13 deletions(-)
  8. diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
  9. index 0da906b..bdfa82b 100644
  10. --- a/arch/arm/boot/dts/imx6sl-warp.dts
  11. +++ b/arch/arm/boot/dts/imx6sl-warp.dts
  12. @@ -61,7 +61,9 @@
  13. usdhc3_pwrseq: usdhc3_pwrseq {
  14. compatible = "mmc-pwrseq-simple";
  15. reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
  16. + <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */
  17. <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
  18. + <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */
  19. <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
  20. <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
  21. };
  22. @@ -73,16 +75,16 @@
  23. status = "okay";
  24. };
  25. -&uart2 {
  26. +&uart3 {
  27. pinctrl-names = "default";
  28. - pinctrl-0 = <&pinctrl_uart2>;
  29. - fsl,uart-has-rtscts;
  30. + pinctrl-0 = <&pinctrl_uart3>;
  31. status = "okay";
  32. };
  33. -&uart3 {
  34. +&uart5 {
  35. pinctrl-names = "default";
  36. - pinctrl-0 = <&pinctrl_uart3>;
  37. + pinctrl-0 = <&pinctrl_uart5>;
  38. + fsl,uart-has-rtscts;
  39. status = "okay";
  40. };
  41. @@ -130,14 +132,6 @@
  42. >;
  43. };
  44. - pinctrl_uart2: uart2grp {
  45. - fsl,pins = <
  46. - MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1
  47. - MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1
  48. - MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1
  49. - MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1
  50. - >;
  51. - };
  52. pinctrl_uart3: uart3grp {
  53. fsl,pins = <
  54. @@ -146,6 +140,15 @@
  55. >;
  56. };
  57. + pinctrl_uart5: uart5grp {
  58. + fsl,pins = <
  59. + MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1
  60. + MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1
  61. + MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1
  62. + MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1
  63. + >;
  64. + };
  65. +
  66. pinctrl_usdhc2: usdhc2grp {
  67. fsl,pins = <
  68. MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059
  69. @@ -158,6 +161,7 @@
  70. MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059
  71. MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059
  72. MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059
  73. + MX6SL_PAD_SD2_RST__SD2_RESET 0x417059
  74. >;
  75. };
  76. @@ -173,6 +177,7 @@
  77. MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9
  78. MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9
  79. MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9
  80. + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9
  81. >;
  82. };
  83. @@ -188,6 +193,7 @@
  84. MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9
  85. MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9
  86. MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9
  87. + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9
  88. >;
  89. };
  90. --
  91. 1.9.1