Config.in 11 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_USE_MMU
  9. bool
  10. config BR2_ARCH_HAS_FDPIC_SUPPORT
  11. bool
  12. choice
  13. prompt "Target Architecture"
  14. default BR2_i386
  15. help
  16. Select the target architecture family to build for.
  17. config BR2_arcle
  18. bool "ARC (little endian)"
  19. select BR2_USE_MMU
  20. help
  21. Synopsys' DesignWare ARC Processor Cores are a family of
  22. 32-bit CPUs that can be used from deeply embedded to high
  23. performance host applications. Little endian.
  24. config BR2_arceb
  25. bool "ARC (big endian)"
  26. select BR2_USE_MMU
  27. help
  28. Synopsys' DesignWare ARC Processor Cores are a family of
  29. 32-bit CPUs that can be used from deeply embedded to high
  30. performance host applications. Big endian.
  31. config BR2_arm
  32. bool "ARM (little endian)"
  33. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  34. help
  35. ARM is a 32-bit reduced instruction set computer (RISC)
  36. instruction set architecture (ISA) developed by ARM Holdings.
  37. Little endian.
  38. http://www.arm.com/
  39. http://en.wikipedia.org/wiki/ARM
  40. config BR2_armeb
  41. bool "ARM (big endian)"
  42. select BR2_USE_MMU
  43. help
  44. ARM is a 32-bit reduced instruction set computer (RISC)
  45. instruction set architecture (ISA) developed by ARM Holdings.
  46. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. help
  53. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  54. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  55. http://en.wikipedia.org/wiki/ARM
  56. config BR2_aarch64_be
  57. bool "AArch64 (big endian)"
  58. select BR2_ARCH_IS_64
  59. help
  60. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  61. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  62. http://en.wikipedia.org/wiki/ARM
  63. config BR2_i386
  64. bool "i386"
  65. select BR2_USE_MMU
  66. help
  67. Intel i386 architecture compatible microprocessor
  68. http://en.wikipedia.org/wiki/I386
  69. config BR2_m68k
  70. bool "m68k"
  71. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  72. help
  73. Motorola 68000 family microprocessor
  74. http://en.wikipedia.org/wiki/M68k
  75. config BR2_microblazeel
  76. bool "Microblaze AXI (little endian)"
  77. select BR2_USE_MMU
  78. help
  79. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
  80. bus based architecture (little endian)
  81. http://www.xilinx.com
  82. http://en.wikipedia.org/wiki/Microblaze
  83. config BR2_microblazebe
  84. bool "Microblaze non-AXI (big endian)"
  85. select BR2_USE_MMU
  86. help
  87. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
  88. bus based architecture (non-AXI, big endian)
  89. http://www.xilinx.com
  90. http://en.wikipedia.org/wiki/Microblaze
  91. config BR2_mips
  92. bool "MIPS (big endian)"
  93. select BR2_USE_MMU
  94. help
  95. MIPS is a RISC microprocessor from MIPS Technologies. Big
  96. endian.
  97. http://www.mips.com/
  98. http://en.wikipedia.org/wiki/MIPS_Technologies
  99. config BR2_mipsel
  100. bool "MIPS (little endian)"
  101. select BR2_USE_MMU
  102. help
  103. MIPS is a RISC microprocessor from MIPS Technologies. Little
  104. endian.
  105. http://www.mips.com/
  106. http://en.wikipedia.org/wiki/MIPS_Technologies
  107. config BR2_mips64
  108. bool "MIPS64 (big endian)"
  109. select BR2_ARCH_IS_64
  110. select BR2_USE_MMU
  111. help
  112. MIPS is a RISC microprocessor from MIPS Technologies. Big
  113. endian.
  114. http://www.mips.com/
  115. http://en.wikipedia.org/wiki/MIPS_Technologies
  116. config BR2_mips64el
  117. bool "MIPS64 (little endian)"
  118. select BR2_ARCH_IS_64
  119. select BR2_USE_MMU
  120. help
  121. MIPS is a RISC microprocessor from MIPS Technologies. Little
  122. endian.
  123. http://www.mips.com/
  124. http://en.wikipedia.org/wiki/MIPS_Technologies
  125. config BR2_nios2
  126. bool "Nios II"
  127. select BR2_USE_MMU
  128. help
  129. Nios II is a soft core processor from Altera Corporation.
  130. http://www.altera.com/
  131. http://en.wikipedia.org/wiki/Nios_II
  132. config BR2_or1k
  133. bool "OpenRISC"
  134. select BR2_USE_MMU
  135. help
  136. OpenRISC is a free and open processor for embedded system.
  137. http://openrisc.io
  138. config BR2_powerpc
  139. bool "PowerPC"
  140. select BR2_USE_MMU
  141. help
  142. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  143. alliance. Big endian.
  144. http://www.power.org/
  145. http://en.wikipedia.org/wiki/Powerpc
  146. config BR2_powerpc64
  147. bool "PowerPC64 (big endian)"
  148. select BR2_ARCH_IS_64
  149. select BR2_USE_MMU
  150. help
  151. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  152. alliance. Big endian.
  153. http://www.power.org/
  154. http://en.wikipedia.org/wiki/Powerpc
  155. config BR2_powerpc64le
  156. bool "PowerPC64 (little endian)"
  157. select BR2_ARCH_IS_64
  158. select BR2_USE_MMU
  159. help
  160. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  161. alliance. Little endian.
  162. http://www.power.org/
  163. http://en.wikipedia.org/wiki/Powerpc
  164. config BR2_riscv
  165. bool "RISCV"
  166. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  167. help
  168. RISC-V is an open, free Instruction Set Architecture created
  169. by the UC Berkeley Architecture Research group and supported
  170. and promoted by RISC-V Foundation.
  171. https://riscv.org/
  172. https://en.wikipedia.org/wiki/RISC-V
  173. config BR2_s390x
  174. bool "s390x"
  175. select BR2_ARCH_IS_64
  176. select BR2_USE_MMU
  177. help
  178. s390x is a big-endian architecture made by IBM.
  179. http://www.ibm.com/
  180. http://en.wikipedia.org/wiki/IBM_System/390
  181. config BR2_sh
  182. bool "SuperH"
  183. select BR2_USE_MMU
  184. help
  185. SuperH (or SH) is a 32-bit reduced instruction set computer
  186. (RISC) instruction set architecture (ISA) developed by
  187. Hitachi.
  188. http://www.hitachi.com/
  189. http://en.wikipedia.org/wiki/SuperH
  190. config BR2_sparc
  191. bool "SPARC"
  192. select BR2_USE_MMU
  193. help
  194. SPARC (from Scalable Processor Architecture) is a RISC
  195. instruction set architecture (ISA) developed by Sun
  196. Microsystems.
  197. http://www.oracle.com/sun
  198. http://en.wikipedia.org/wiki/Sparc
  199. config BR2_sparc64
  200. bool "SPARC64"
  201. select BR2_ARCH_IS_64
  202. select BR2_USE_MMU
  203. help
  204. SPARC (from Scalable Processor Architecture) is a RISC
  205. instruction set architecture (ISA) developed by Sun
  206. Microsystems.
  207. http://www.oracle.com/sun
  208. http://en.wikipedia.org/wiki/Sparc
  209. config BR2_x86_64
  210. bool "x86_64"
  211. select BR2_ARCH_IS_64
  212. select BR2_USE_MMU
  213. help
  214. x86-64 is an extension of the x86 instruction set (Intel i386
  215. architecture compatible microprocessor).
  216. http://en.wikipedia.org/wiki/X86_64
  217. config BR2_xtensa
  218. bool "Xtensa"
  219. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  220. help
  221. Xtensa is a Tensilica processor IP architecture.
  222. http://en.wikipedia.org/wiki/Xtensa
  223. http://www.tensilica.com/
  224. endchoice
  225. # For some architectures or specific cores, our internal toolchain
  226. # backend is not suitable (like, missing support in upstream gcc, or
  227. # no ChipCo fork exists...)
  228. config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  229. bool
  230. config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
  231. bool
  232. default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  233. # The following symbols are selected by the individual
  234. # Config.in.$ARCH files
  235. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  236. bool
  237. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  238. bool
  239. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  240. config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  241. bool
  242. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  243. config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  244. bool
  245. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  246. config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  247. bool
  248. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  249. config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  250. bool
  251. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  252. config BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  253. bool
  254. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  255. config BR2_ARCH_NEEDS_GCC_AT_LEAST_10
  256. bool
  257. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  258. config BR2_ARCH_NEEDS_GCC_AT_LEAST_11
  259. bool
  260. select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
  261. config BR2_ARCH_NEEDS_GCC_AT_LEAST_12
  262. bool
  263. select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
  264. config BR2_ARCH_NEEDS_GCC_AT_LEAST_13
  265. bool
  266. select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
  267. config BR2_ARCH_NEEDS_GCC_AT_LEAST_14
  268. bool
  269. select BR2_ARCH_NEEDS_GCC_AT_LEAST_13
  270. config BR2_ARCH_NEEDS_GCC_AT_LEAST_15
  271. bool
  272. select BR2_ARCH_NEEDS_GCC_AT_LEAST_14
  273. # The following string values are defined by the individual
  274. # Config.in.$ARCH files
  275. config BR2_ARCH
  276. string
  277. config BR2_NORMALIZED_ARCH
  278. string
  279. config BR2_ENDIAN
  280. string
  281. config BR2_GCC_TARGET_ARCH
  282. string
  283. config BR2_GCC_TARGET_ABI
  284. string
  285. config BR2_GCC_TARGET_NAN
  286. string
  287. config BR2_GCC_TARGET_FP32_MODE
  288. string
  289. config BR2_GCC_TARGET_CPU
  290. string
  291. # The value of this option will be passed as --with-fpu=<value> when
  292. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  293. # wrapper (external toolchain)
  294. config BR2_GCC_TARGET_FPU
  295. string
  296. # The value of this option will be passed as --with-float=<value> when
  297. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  298. # wrapper (external toolchain)
  299. config BR2_GCC_TARGET_FLOAT_ABI
  300. string
  301. # The value of this option will be passed as --with-mode=<value> when
  302. # building gcc (internal backend) or -m<value> in the toolchain
  303. # wrapper (external toolchain)
  304. config BR2_GCC_TARGET_MODE
  305. string
  306. # Must be selected by binary formats that support shared libraries.
  307. config BR2_BINFMT_SUPPORTS_SHARED
  308. bool
  309. # Must match the name of the architecture from readelf point of view,
  310. # i.e the "Machine:" field of readelf output. See get_machine_name()
  311. # in binutils/readelf.c for the list of possible values.
  312. config BR2_READELF_ARCH_NAME
  313. string
  314. if BR2_arcle || BR2_arceb
  315. source "arch/Config.in.arc"
  316. endif
  317. if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
  318. source "arch/Config.in.arm"
  319. endif
  320. if BR2_m68k
  321. source "arch/Config.in.m68k"
  322. endif
  323. if BR2_microblazeel || BR2_microblazebe
  324. source "arch/Config.in.microblaze"
  325. endif
  326. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  327. source "arch/Config.in.mips"
  328. endif
  329. if BR2_nios2
  330. source "arch/Config.in.nios2"
  331. endif
  332. if BR2_or1k
  333. source "arch/Config.in.or1k"
  334. endif
  335. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  336. source "arch/Config.in.powerpc"
  337. endif
  338. if BR2_riscv
  339. source "arch/Config.in.riscv"
  340. endif
  341. if BR2_s390x
  342. source "arch/Config.in.s390x"
  343. endif
  344. if BR2_sh
  345. source "arch/Config.in.sh"
  346. endif
  347. if BR2_sparc || BR2_sparc64
  348. source "arch/Config.in.sparc"
  349. endif
  350. if BR2_i386 || BR2_x86_64
  351. source "arch/Config.in.x86"
  352. endif
  353. if BR2_xtensa
  354. source "arch/Config.in.xtensa"
  355. endif
  356. # Set up target binary format
  357. choice
  358. prompt "Target Binary Format"
  359. default BR2_BINFMT_ELF if BR2_USE_MMU
  360. default BR2_BINFMT_FLAT
  361. config BR2_BINFMT_ELF
  362. bool "ELF"
  363. depends on BR2_USE_MMU
  364. select BR2_BINFMT_SUPPORTS_SHARED
  365. help
  366. ELF (Executable and Linkable Format) is a format for libraries
  367. and executables used across different architectures and
  368. operating systems.
  369. config BR2_BINFMT_FDPIC
  370. bool "FDPIC"
  371. depends on BR2_ARCH_HAS_FDPIC_SUPPORT
  372. select BR2_BINFMT_SUPPORTS_SHARED
  373. help
  374. ELF FDPIC binaries are based on ELF, but allow the individual
  375. load segments of a binary to be located in memory
  376. independently of each other. This makes this format ideal for
  377. use in environments where no MMU is available.
  378. config BR2_BINFMT_FLAT
  379. bool "FLAT"
  380. depends on !BR2_USE_MMU
  381. help
  382. FLAT binary is a relatively simple and lightweight executable
  383. format based on the original a.out format. It is widely used
  384. in environment where no MMU is available.
  385. endchoice
  386. endmenu # Target options