Config.in 12 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. choice
  13. prompt "Target Architecture"
  14. default BR2_i386
  15. help
  16. Select the target architecture family to build for.
  17. config BR2_arcle
  18. bool "ARC (little endian)"
  19. select BR2_ARCH_HAS_MMU_MANDATORY
  20. help
  21. Synopsys' DesignWare ARC Processor Cores are a family of
  22. 32-bit CPUs that can be used from deeply embedded to high
  23. performance host applications. Little endian.
  24. config BR2_arceb
  25. bool "ARC (big endian)"
  26. select BR2_ARCH_HAS_MMU_MANDATORY
  27. help
  28. Synopsys' DesignWare ARC Processor Cores are a family of
  29. 32-bit CPUs that can be used from deeply embedded to high
  30. performance host applications. Big endian.
  31. config BR2_arm
  32. bool "ARM (little endian)"
  33. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  34. help
  35. ARM is a 32-bit reduced instruction set computer (RISC)
  36. instruction set architecture (ISA) developed by ARM Holdings.
  37. Little endian.
  38. http://www.arm.com/
  39. http://en.wikipedia.org/wiki/ARM
  40. config BR2_armeb
  41. bool "ARM (big endian)"
  42. select BR2_ARCH_HAS_MMU_MANDATORY
  43. help
  44. ARM is a 32-bit reduced instruction set computer (RISC)
  45. instruction set architecture (ISA) developed by ARM Holdings.
  46. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. help
  53. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  54. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  55. http://en.wikipedia.org/wiki/ARM
  56. config BR2_aarch64_be
  57. bool "AArch64 (big endian)"
  58. select BR2_ARCH_IS_64
  59. help
  60. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  61. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  62. http://en.wikipedia.org/wiki/ARM
  63. config BR2_csky
  64. bool "csky"
  65. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  66. select BR2_ARCH_HAS_MMU_MANDATORY
  67. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  68. help
  69. csky is processor IP from china.
  70. http://www.c-sky.com/
  71. http://www.github.com/c-sky
  72. config BR2_i386
  73. bool "i386"
  74. select BR2_ARCH_HAS_MMU_MANDATORY
  75. help
  76. Intel i386 architecture compatible microprocessor
  77. http://en.wikipedia.org/wiki/I386
  78. config BR2_m68k
  79. bool "m68k"
  80. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  81. help
  82. Motorola 68000 family microprocessor
  83. http://en.wikipedia.org/wiki/M68k
  84. config BR2_microblazeel
  85. bool "Microblaze AXI (little endian)"
  86. select BR2_ARCH_HAS_MMU_MANDATORY
  87. help
  88. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
  89. bus based architecture (little endian)
  90. http://www.xilinx.com
  91. http://en.wikipedia.org/wiki/Microblaze
  92. config BR2_microblazebe
  93. bool "Microblaze non-AXI (big endian)"
  94. select BR2_ARCH_HAS_MMU_MANDATORY
  95. help
  96. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
  97. bus based architecture (non-AXI, big endian)
  98. http://www.xilinx.com
  99. http://en.wikipedia.org/wiki/Microblaze
  100. config BR2_mips
  101. bool "MIPS (big endian)"
  102. select BR2_ARCH_HAS_MMU_MANDATORY
  103. help
  104. MIPS is a RISC microprocessor from MIPS Technologies. Big
  105. endian.
  106. http://www.mips.com/
  107. http://en.wikipedia.org/wiki/MIPS_Technologies
  108. config BR2_mipsel
  109. bool "MIPS (little endian)"
  110. select BR2_ARCH_HAS_MMU_MANDATORY
  111. help
  112. MIPS is a RISC microprocessor from MIPS Technologies. Little
  113. endian.
  114. http://www.mips.com/
  115. http://en.wikipedia.org/wiki/MIPS_Technologies
  116. config BR2_mips64
  117. bool "MIPS64 (big endian)"
  118. select BR2_ARCH_IS_64
  119. select BR2_ARCH_HAS_MMU_MANDATORY
  120. help
  121. MIPS is a RISC microprocessor from MIPS Technologies. Big
  122. endian.
  123. http://www.mips.com/
  124. http://en.wikipedia.org/wiki/MIPS_Technologies
  125. config BR2_mips64el
  126. bool "MIPS64 (little endian)"
  127. select BR2_ARCH_IS_64
  128. select BR2_ARCH_HAS_MMU_MANDATORY
  129. help
  130. MIPS is a RISC microprocessor from MIPS Technologies. Little
  131. endian.
  132. http://www.mips.com/
  133. http://en.wikipedia.org/wiki/MIPS_Technologies
  134. config BR2_nds32
  135. bool "nds32"
  136. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  137. select BR2_ARCH_HAS_MMU_MANDATORY
  138. help
  139. nds32 is a 32-bit architecture developed by Andes Technology.
  140. https://en.wikipedia.org/wiki/Andes_Technology
  141. config BR2_nios2
  142. bool "Nios II"
  143. select BR2_ARCH_HAS_MMU_MANDATORY
  144. help
  145. Nios II is a soft core processor from Altera Corporation.
  146. http://www.altera.com/
  147. http://en.wikipedia.org/wiki/Nios_II
  148. config BR2_or1k
  149. bool "OpenRISC"
  150. select BR2_ARCH_HAS_MMU_MANDATORY
  151. help
  152. OpenRISC is a free and open processor for embedded system.
  153. http://openrisc.io
  154. config BR2_powerpc
  155. bool "PowerPC"
  156. select BR2_ARCH_HAS_MMU_MANDATORY
  157. help
  158. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  159. alliance. Big endian.
  160. http://www.power.org/
  161. http://en.wikipedia.org/wiki/Powerpc
  162. config BR2_powerpc64
  163. bool "PowerPC64 (big endian)"
  164. select BR2_ARCH_IS_64
  165. select BR2_ARCH_HAS_MMU_MANDATORY
  166. help
  167. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  168. alliance. Big endian.
  169. http://www.power.org/
  170. http://en.wikipedia.org/wiki/Powerpc
  171. config BR2_powerpc64le
  172. bool "PowerPC64 (little endian)"
  173. select BR2_ARCH_IS_64
  174. select BR2_ARCH_HAS_MMU_MANDATORY
  175. help
  176. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  177. alliance. Little endian.
  178. http://www.power.org/
  179. http://en.wikipedia.org/wiki/Powerpc
  180. config BR2_riscv
  181. bool "RISCV"
  182. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  183. help
  184. RISC-V is an open, free Instruction Set Architecture created
  185. by the UC Berkeley Architecture Research group and supported
  186. and promoted by RISC-V Foundation.
  187. https://riscv.org/
  188. https://en.wikipedia.org/wiki/RISC-V
  189. config BR2_s390x
  190. bool "s390x"
  191. select BR2_ARCH_IS_64
  192. select BR2_ARCH_HAS_MMU_MANDATORY
  193. help
  194. s390x is a big-endian architecture made by IBM.
  195. http://www.ibm.com/
  196. http://en.wikipedia.org/wiki/IBM_System/390
  197. config BR2_sh
  198. bool "SuperH"
  199. select BR2_ARCH_HAS_MMU_MANDATORY
  200. help
  201. SuperH (or SH) is a 32-bit reduced instruction set computer
  202. (RISC) instruction set architecture (ISA) developed by
  203. Hitachi.
  204. http://www.hitachi.com/
  205. http://en.wikipedia.org/wiki/SuperH
  206. config BR2_sparc
  207. bool "SPARC"
  208. select BR2_ARCH_HAS_MMU_MANDATORY
  209. help
  210. SPARC (from Scalable Processor Architecture) is a RISC
  211. instruction set architecture (ISA) developed by Sun
  212. Microsystems.
  213. http://www.oracle.com/sun
  214. http://en.wikipedia.org/wiki/Sparc
  215. config BR2_sparc64
  216. bool "SPARC64"
  217. select BR2_ARCH_IS_64
  218. select BR2_ARCH_HAS_MMU_MANDATORY
  219. help
  220. SPARC (from Scalable Processor Architecture) is a RISC
  221. instruction set architecture (ISA) developed by Sun
  222. Microsystems.
  223. http://www.oracle.com/sun
  224. http://en.wikipedia.org/wiki/Sparc
  225. config BR2_x86_64
  226. bool "x86_64"
  227. select BR2_ARCH_IS_64
  228. select BR2_ARCH_HAS_MMU_MANDATORY
  229. help
  230. x86-64 is an extension of the x86 instruction set (Intel i386
  231. architecture compatible microprocessor).
  232. http://en.wikipedia.org/wiki/X86_64
  233. config BR2_xtensa
  234. bool "Xtensa"
  235. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  236. help
  237. Xtensa is a Tensilica processor IP architecture.
  238. http://en.wikipedia.org/wiki/Xtensa
  239. http://www.tensilica.com/
  240. endchoice
  241. # For some architectures or specific cores, our internal toolchain
  242. # backend is not suitable (like, missing support in upstream gcc, or
  243. # no ChipCo fork exists...)
  244. config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  245. bool
  246. config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
  247. bool
  248. default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  249. # The following symbols are selected by the individual
  250. # Config.in.$ARCH files
  251. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  252. bool
  253. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  254. bool
  255. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  256. config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  257. bool
  258. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  259. config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  260. bool
  261. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  262. config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  263. bool
  264. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  265. config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  266. bool
  267. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  268. config BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  269. bool
  270. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  271. config BR2_ARCH_NEEDS_GCC_AT_LEAST_10
  272. bool
  273. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  274. config BR2_ARCH_NEEDS_GCC_AT_LEAST_11
  275. bool
  276. select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
  277. # The following string values are defined by the individual
  278. # Config.in.$ARCH files
  279. config BR2_ARCH
  280. string
  281. config BR2_NORMALIZED_ARCH
  282. string
  283. config BR2_ENDIAN
  284. string
  285. config BR2_GCC_TARGET_ARCH
  286. string
  287. config BR2_GCC_TARGET_ABI
  288. string
  289. config BR2_GCC_TARGET_NAN
  290. string
  291. config BR2_GCC_TARGET_FP32_MODE
  292. string
  293. config BR2_GCC_TARGET_CPU
  294. string
  295. # The value of this option will be passed as --with-fpu=<value> when
  296. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  297. # wrapper (external toolchain)
  298. config BR2_GCC_TARGET_FPU
  299. string
  300. # The value of this option will be passed as --with-float=<value> when
  301. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  302. # wrapper (external toolchain)
  303. config BR2_GCC_TARGET_FLOAT_ABI
  304. string
  305. # The value of this option will be passed as --with-mode=<value> when
  306. # building gcc (internal backend) or -m<value> in the toolchain
  307. # wrapper (external toolchain)
  308. config BR2_GCC_TARGET_MODE
  309. string
  310. # Must be selected by binary formats that support shared libraries.
  311. config BR2_BINFMT_SUPPORTS_SHARED
  312. bool
  313. # Must match the name of the architecture from readelf point of view,
  314. # i.e the "Machine:" field of readelf output. See get_machine_name()
  315. # in binutils/readelf.c for the list of possible values.
  316. config BR2_READELF_ARCH_NAME
  317. string
  318. # Set up target binary format
  319. choice
  320. prompt "Target Binary Format"
  321. default BR2_BINFMT_ELF if BR2_USE_MMU
  322. default BR2_BINFMT_FLAT
  323. config BR2_BINFMT_ELF
  324. bool "ELF"
  325. depends on BR2_USE_MMU
  326. select BR2_BINFMT_SUPPORTS_SHARED
  327. help
  328. ELF (Executable and Linkable Format) is a format for libraries
  329. and executables used across different architectures and
  330. operating systems.
  331. config BR2_BINFMT_FLAT
  332. bool "FLAT"
  333. depends on !BR2_USE_MMU
  334. help
  335. FLAT binary is a relatively simple and lightweight executable
  336. format based on the original a.out format. It is widely used
  337. in environment where no MMU is available.
  338. endchoice
  339. # Set up flat binary type
  340. choice
  341. prompt "FLAT Binary type"
  342. default BR2_BINFMT_FLAT_ONE
  343. depends on BR2_BINFMT_FLAT
  344. config BR2_BINFMT_FLAT_ONE
  345. bool "One memory region"
  346. help
  347. All segments are linked into one memory region.
  348. config BR2_BINFMT_FLAT_SHARED
  349. bool "Shared binary"
  350. depends on BR2_m68k
  351. # Even though this really generates shared binaries, there is no libdl
  352. # and dlopen() cannot be used. So packages that require shared
  353. # libraries cannot be built. Therefore, we don't select
  354. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  355. # Although this adds -static to the compilation, that's not a problem
  356. # because the -mid-shared-library option overrides it.
  357. help
  358. Allow to load and link indiviual FLAT binaries at run time.
  359. endchoice
  360. if BR2_arcle || BR2_arceb
  361. source "arch/Config.in.arc"
  362. endif
  363. if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
  364. source "arch/Config.in.arm"
  365. endif
  366. if BR2_csky
  367. source "arch/Config.in.csky"
  368. endif
  369. if BR2_m68k
  370. source "arch/Config.in.m68k"
  371. endif
  372. if BR2_microblazeel || BR2_microblazebe
  373. source "arch/Config.in.microblaze"
  374. endif
  375. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  376. source "arch/Config.in.mips"
  377. endif
  378. if BR2_nds32
  379. source "arch/Config.in.nds32"
  380. endif
  381. if BR2_nios2
  382. source "arch/Config.in.nios2"
  383. endif
  384. if BR2_or1k
  385. source "arch/Config.in.or1k"
  386. endif
  387. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  388. source "arch/Config.in.powerpc"
  389. endif
  390. if BR2_riscv
  391. source "arch/Config.in.riscv"
  392. endif
  393. if BR2_s390x
  394. source "arch/Config.in.s390x"
  395. endif
  396. if BR2_sh
  397. source "arch/Config.in.sh"
  398. endif
  399. if BR2_sparc || BR2_sparc64
  400. source "arch/Config.in.sparc"
  401. endif
  402. if BR2_i386 || BR2_x86_64
  403. source "arch/Config.in.x86"
  404. endif
  405. if BR2_xtensa
  406. source "arch/Config.in.xtensa"
  407. endif
  408. endmenu # Target options