intel-pt.c 65 KB

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  1. /*
  2. * intel_pt.c: Intel Processor Trace support
  3. * Copyright (c) 2013-2015, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #include <inttypes.h>
  16. #include <stdio.h>
  17. #include <stdbool.h>
  18. #include <errno.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include "../perf.h"
  22. #include "session.h"
  23. #include "machine.h"
  24. #include "memswap.h"
  25. #include "sort.h"
  26. #include "tool.h"
  27. #include "event.h"
  28. #include "evlist.h"
  29. #include "evsel.h"
  30. #include "map.h"
  31. #include "color.h"
  32. #include "util.h"
  33. #include "thread.h"
  34. #include "thread-stack.h"
  35. #include "symbol.h"
  36. #include "callchain.h"
  37. #include "dso.h"
  38. #include "debug.h"
  39. #include "auxtrace.h"
  40. #include "tsc.h"
  41. #include "intel-pt.h"
  42. #include "config.h"
  43. #include "intel-pt-decoder/intel-pt-log.h"
  44. #include "intel-pt-decoder/intel-pt-decoder.h"
  45. #include "intel-pt-decoder/intel-pt-insn-decoder.h"
  46. #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
  47. #define MAX_TIMESTAMP (~0ULL)
  48. struct intel_pt {
  49. struct auxtrace auxtrace;
  50. struct auxtrace_queues queues;
  51. struct auxtrace_heap heap;
  52. u32 auxtrace_type;
  53. struct perf_session *session;
  54. struct machine *machine;
  55. struct perf_evsel *switch_evsel;
  56. struct thread *unknown_thread;
  57. bool timeless_decoding;
  58. bool sampling_mode;
  59. bool snapshot_mode;
  60. bool per_cpu_mmaps;
  61. bool have_tsc;
  62. bool data_queued;
  63. bool est_tsc;
  64. bool sync_switch;
  65. bool mispred_all;
  66. int have_sched_switch;
  67. u32 pmu_type;
  68. u64 kernel_start;
  69. u64 switch_ip;
  70. u64 ptss_ip;
  71. struct perf_tsc_conversion tc;
  72. bool cap_user_time_zero;
  73. struct itrace_synth_opts synth_opts;
  74. bool sample_instructions;
  75. u64 instructions_sample_type;
  76. u64 instructions_id;
  77. bool sample_branches;
  78. u32 branches_filter;
  79. u64 branches_sample_type;
  80. u64 branches_id;
  81. bool sample_transactions;
  82. u64 transactions_sample_type;
  83. u64 transactions_id;
  84. bool sample_ptwrites;
  85. u64 ptwrites_sample_type;
  86. u64 ptwrites_id;
  87. bool sample_pwr_events;
  88. u64 pwr_events_sample_type;
  89. u64 mwait_id;
  90. u64 pwre_id;
  91. u64 exstop_id;
  92. u64 pwrx_id;
  93. u64 cbr_id;
  94. u64 tsc_bit;
  95. u64 mtc_bit;
  96. u64 mtc_freq_bits;
  97. u32 tsc_ctc_ratio_n;
  98. u32 tsc_ctc_ratio_d;
  99. u64 cyc_bit;
  100. u64 noretcomp_bit;
  101. unsigned max_non_turbo_ratio;
  102. unsigned cbr2khz;
  103. unsigned long num_events;
  104. char *filter;
  105. struct addr_filters filts;
  106. };
  107. enum switch_state {
  108. INTEL_PT_SS_NOT_TRACING,
  109. INTEL_PT_SS_UNKNOWN,
  110. INTEL_PT_SS_TRACING,
  111. INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
  112. INTEL_PT_SS_EXPECTING_SWITCH_IP,
  113. };
  114. struct intel_pt_queue {
  115. struct intel_pt *pt;
  116. unsigned int queue_nr;
  117. struct auxtrace_buffer *buffer;
  118. struct auxtrace_buffer *old_buffer;
  119. void *decoder;
  120. const struct intel_pt_state *state;
  121. struct ip_callchain *chain;
  122. struct branch_stack *last_branch;
  123. struct branch_stack *last_branch_rb;
  124. size_t last_branch_pos;
  125. union perf_event *event_buf;
  126. bool on_heap;
  127. bool stop;
  128. bool step_through_buffers;
  129. bool use_buffer_pid_tid;
  130. bool sync_switch;
  131. pid_t pid, tid;
  132. int cpu;
  133. int switch_state;
  134. pid_t next_tid;
  135. struct thread *thread;
  136. bool exclude_kernel;
  137. bool have_sample;
  138. u64 time;
  139. u64 timestamp;
  140. u32 flags;
  141. u16 insn_len;
  142. u64 last_insn_cnt;
  143. char insn[INTEL_PT_INSN_BUF_SZ];
  144. };
  145. static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
  146. unsigned char *buf, size_t len)
  147. {
  148. struct intel_pt_pkt packet;
  149. size_t pos = 0;
  150. int ret, pkt_len, i;
  151. char desc[INTEL_PT_PKT_DESC_MAX];
  152. const char *color = PERF_COLOR_BLUE;
  153. color_fprintf(stdout, color,
  154. ". ... Intel Processor Trace data: size %zu bytes\n",
  155. len);
  156. while (len) {
  157. ret = intel_pt_get_packet(buf, len, &packet);
  158. if (ret > 0)
  159. pkt_len = ret;
  160. else
  161. pkt_len = 1;
  162. printf(".");
  163. color_fprintf(stdout, color, " %08x: ", pos);
  164. for (i = 0; i < pkt_len; i++)
  165. color_fprintf(stdout, color, " %02x", buf[i]);
  166. for (; i < 16; i++)
  167. color_fprintf(stdout, color, " ");
  168. if (ret > 0) {
  169. ret = intel_pt_pkt_desc(&packet, desc,
  170. INTEL_PT_PKT_DESC_MAX);
  171. if (ret > 0)
  172. color_fprintf(stdout, color, " %s\n", desc);
  173. } else {
  174. color_fprintf(stdout, color, " Bad packet!\n");
  175. }
  176. pos += pkt_len;
  177. buf += pkt_len;
  178. len -= pkt_len;
  179. }
  180. }
  181. static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
  182. size_t len)
  183. {
  184. printf(".\n");
  185. intel_pt_dump(pt, buf, len);
  186. }
  187. static void intel_pt_log_event(union perf_event *event)
  188. {
  189. FILE *f = intel_pt_log_fp();
  190. if (!intel_pt_enable_logging || !f)
  191. return;
  192. perf_event__fprintf(event, f);
  193. }
  194. static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
  195. struct auxtrace_buffer *b)
  196. {
  197. bool consecutive = false;
  198. void *start;
  199. start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
  200. pt->have_tsc, &consecutive);
  201. if (!start)
  202. return -EINVAL;
  203. b->use_size = b->data + b->size - start;
  204. b->use_data = start;
  205. if (b->use_size && consecutive)
  206. b->consecutive = true;
  207. return 0;
  208. }
  209. /* This function assumes data is processed sequentially only */
  210. static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
  211. {
  212. struct intel_pt_queue *ptq = data;
  213. struct auxtrace_buffer *buffer = ptq->buffer;
  214. struct auxtrace_buffer *old_buffer = ptq->old_buffer;
  215. struct auxtrace_queue *queue;
  216. bool might_overlap;
  217. if (ptq->stop) {
  218. b->len = 0;
  219. return 0;
  220. }
  221. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  222. buffer = auxtrace_buffer__next(queue, buffer);
  223. if (!buffer) {
  224. if (old_buffer)
  225. auxtrace_buffer__drop_data(old_buffer);
  226. b->len = 0;
  227. return 0;
  228. }
  229. ptq->buffer = buffer;
  230. if (!buffer->data) {
  231. int fd = perf_data__fd(ptq->pt->session->data);
  232. buffer->data = auxtrace_buffer__get_data(buffer, fd);
  233. if (!buffer->data)
  234. return -ENOMEM;
  235. }
  236. might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
  237. if (might_overlap && !buffer->consecutive && old_buffer &&
  238. intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
  239. return -ENOMEM;
  240. if (buffer->use_data) {
  241. b->len = buffer->use_size;
  242. b->buf = buffer->use_data;
  243. } else {
  244. b->len = buffer->size;
  245. b->buf = buffer->data;
  246. }
  247. b->ref_timestamp = buffer->reference;
  248. if (!old_buffer || (might_overlap && !buffer->consecutive)) {
  249. b->consecutive = false;
  250. b->trace_nr = buffer->buffer_nr + 1;
  251. } else {
  252. b->consecutive = true;
  253. }
  254. if (ptq->step_through_buffers)
  255. ptq->stop = true;
  256. if (b->len) {
  257. if (old_buffer)
  258. auxtrace_buffer__drop_data(old_buffer);
  259. ptq->old_buffer = buffer;
  260. } else {
  261. auxtrace_buffer__drop_data(buffer);
  262. return intel_pt_get_trace(b, data);
  263. }
  264. return 0;
  265. }
  266. struct intel_pt_cache_entry {
  267. struct auxtrace_cache_entry entry;
  268. u64 insn_cnt;
  269. u64 byte_cnt;
  270. enum intel_pt_insn_op op;
  271. enum intel_pt_insn_branch branch;
  272. int length;
  273. int32_t rel;
  274. char insn[INTEL_PT_INSN_BUF_SZ];
  275. };
  276. static int intel_pt_config_div(const char *var, const char *value, void *data)
  277. {
  278. int *d = data;
  279. long val;
  280. if (!strcmp(var, "intel-pt.cache-divisor")) {
  281. val = strtol(value, NULL, 0);
  282. if (val > 0 && val <= INT_MAX)
  283. *d = val;
  284. }
  285. return 0;
  286. }
  287. static int intel_pt_cache_divisor(void)
  288. {
  289. static int d;
  290. if (d)
  291. return d;
  292. perf_config(intel_pt_config_div, &d);
  293. if (!d)
  294. d = 64;
  295. return d;
  296. }
  297. static unsigned int intel_pt_cache_size(struct dso *dso,
  298. struct machine *machine)
  299. {
  300. off_t size;
  301. size = dso__data_size(dso, machine);
  302. size /= intel_pt_cache_divisor();
  303. if (size < 1000)
  304. return 10;
  305. if (size > (1 << 21))
  306. return 21;
  307. return 32 - __builtin_clz(size);
  308. }
  309. static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
  310. struct machine *machine)
  311. {
  312. struct auxtrace_cache *c;
  313. unsigned int bits;
  314. if (dso->auxtrace_cache)
  315. return dso->auxtrace_cache;
  316. bits = intel_pt_cache_size(dso, machine);
  317. /* Ignoring cache creation failure */
  318. c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
  319. dso->auxtrace_cache = c;
  320. return c;
  321. }
  322. static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
  323. u64 offset, u64 insn_cnt, u64 byte_cnt,
  324. struct intel_pt_insn *intel_pt_insn)
  325. {
  326. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  327. struct intel_pt_cache_entry *e;
  328. int err;
  329. if (!c)
  330. return -ENOMEM;
  331. e = auxtrace_cache__alloc_entry(c);
  332. if (!e)
  333. return -ENOMEM;
  334. e->insn_cnt = insn_cnt;
  335. e->byte_cnt = byte_cnt;
  336. e->op = intel_pt_insn->op;
  337. e->branch = intel_pt_insn->branch;
  338. e->length = intel_pt_insn->length;
  339. e->rel = intel_pt_insn->rel;
  340. memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
  341. err = auxtrace_cache__add(c, offset, &e->entry);
  342. if (err)
  343. auxtrace_cache__free_entry(c, e);
  344. return err;
  345. }
  346. static struct intel_pt_cache_entry *
  347. intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
  348. {
  349. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  350. if (!c)
  351. return NULL;
  352. return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
  353. }
  354. static inline u8 intel_pt_cpumode(struct intel_pt *pt, uint64_t ip)
  355. {
  356. return ip >= pt->kernel_start ?
  357. PERF_RECORD_MISC_KERNEL :
  358. PERF_RECORD_MISC_USER;
  359. }
  360. static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
  361. uint64_t *insn_cnt_ptr, uint64_t *ip,
  362. uint64_t to_ip, uint64_t max_insn_cnt,
  363. void *data)
  364. {
  365. struct intel_pt_queue *ptq = data;
  366. struct machine *machine = ptq->pt->machine;
  367. struct thread *thread;
  368. struct addr_location al;
  369. unsigned char buf[INTEL_PT_INSN_BUF_SZ];
  370. ssize_t len;
  371. int x86_64;
  372. u8 cpumode;
  373. u64 offset, start_offset, start_ip;
  374. u64 insn_cnt = 0;
  375. bool one_map = true;
  376. intel_pt_insn->length = 0;
  377. if (to_ip && *ip == to_ip)
  378. goto out_no_cache;
  379. cpumode = intel_pt_cpumode(ptq->pt, *ip);
  380. thread = ptq->thread;
  381. if (!thread) {
  382. if (cpumode != PERF_RECORD_MISC_KERNEL)
  383. return -EINVAL;
  384. thread = ptq->pt->unknown_thread;
  385. }
  386. while (1) {
  387. if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso)
  388. return -EINVAL;
  389. if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
  390. dso__data_status_seen(al.map->dso,
  391. DSO_DATA_STATUS_SEEN_ITRACE))
  392. return -ENOENT;
  393. offset = al.map->map_ip(al.map, *ip);
  394. if (!to_ip && one_map) {
  395. struct intel_pt_cache_entry *e;
  396. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  397. if (e &&
  398. (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
  399. *insn_cnt_ptr = e->insn_cnt;
  400. *ip += e->byte_cnt;
  401. intel_pt_insn->op = e->op;
  402. intel_pt_insn->branch = e->branch;
  403. intel_pt_insn->length = e->length;
  404. intel_pt_insn->rel = e->rel;
  405. memcpy(intel_pt_insn->buf, e->insn,
  406. INTEL_PT_INSN_BUF_SZ);
  407. intel_pt_log_insn_no_data(intel_pt_insn, *ip);
  408. return 0;
  409. }
  410. }
  411. start_offset = offset;
  412. start_ip = *ip;
  413. /* Load maps to ensure dso->is_64_bit has been updated */
  414. map__load(al.map);
  415. x86_64 = al.map->dso->is_64_bit;
  416. while (1) {
  417. len = dso__data_read_offset(al.map->dso, machine,
  418. offset, buf,
  419. INTEL_PT_INSN_BUF_SZ);
  420. if (len <= 0)
  421. return -EINVAL;
  422. if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
  423. return -EINVAL;
  424. intel_pt_log_insn(intel_pt_insn, *ip);
  425. insn_cnt += 1;
  426. if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
  427. goto out;
  428. if (max_insn_cnt && insn_cnt >= max_insn_cnt)
  429. goto out_no_cache;
  430. *ip += intel_pt_insn->length;
  431. if (to_ip && *ip == to_ip)
  432. goto out_no_cache;
  433. if (*ip >= al.map->end)
  434. break;
  435. offset += intel_pt_insn->length;
  436. }
  437. one_map = false;
  438. }
  439. out:
  440. *insn_cnt_ptr = insn_cnt;
  441. if (!one_map)
  442. goto out_no_cache;
  443. /*
  444. * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
  445. * entries.
  446. */
  447. if (to_ip) {
  448. struct intel_pt_cache_entry *e;
  449. e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
  450. if (e)
  451. return 0;
  452. }
  453. /* Ignore cache errors */
  454. intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
  455. *ip - start_ip, intel_pt_insn);
  456. return 0;
  457. out_no_cache:
  458. *insn_cnt_ptr = insn_cnt;
  459. return 0;
  460. }
  461. static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
  462. uint64_t offset, const char *filename)
  463. {
  464. struct addr_filter *filt;
  465. bool have_filter = false;
  466. bool hit_tracestop = false;
  467. bool hit_filter = false;
  468. list_for_each_entry(filt, &pt->filts.head, list) {
  469. if (filt->start)
  470. have_filter = true;
  471. if ((filename && !filt->filename) ||
  472. (!filename && filt->filename) ||
  473. (filename && strcmp(filename, filt->filename)))
  474. continue;
  475. if (!(offset >= filt->addr && offset < filt->addr + filt->size))
  476. continue;
  477. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
  478. ip, offset, filename ? filename : "[kernel]",
  479. filt->start ? "filter" : "stop",
  480. filt->addr, filt->size);
  481. if (filt->start)
  482. hit_filter = true;
  483. else
  484. hit_tracestop = true;
  485. }
  486. if (!hit_tracestop && !hit_filter)
  487. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
  488. ip, offset, filename ? filename : "[kernel]");
  489. return hit_tracestop || (have_filter && !hit_filter);
  490. }
  491. static int __intel_pt_pgd_ip(uint64_t ip, void *data)
  492. {
  493. struct intel_pt_queue *ptq = data;
  494. struct thread *thread;
  495. struct addr_location al;
  496. u8 cpumode;
  497. u64 offset;
  498. if (ip >= ptq->pt->kernel_start)
  499. return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
  500. cpumode = PERF_RECORD_MISC_USER;
  501. thread = ptq->thread;
  502. if (!thread)
  503. return -EINVAL;
  504. if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso)
  505. return -EINVAL;
  506. offset = al.map->map_ip(al.map, ip);
  507. return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
  508. al.map->dso->long_name);
  509. }
  510. static bool intel_pt_pgd_ip(uint64_t ip, void *data)
  511. {
  512. return __intel_pt_pgd_ip(ip, data) > 0;
  513. }
  514. static bool intel_pt_get_config(struct intel_pt *pt,
  515. struct perf_event_attr *attr, u64 *config)
  516. {
  517. if (attr->type == pt->pmu_type) {
  518. if (config)
  519. *config = attr->config;
  520. return true;
  521. }
  522. return false;
  523. }
  524. static bool intel_pt_exclude_kernel(struct intel_pt *pt)
  525. {
  526. struct perf_evsel *evsel;
  527. evlist__for_each_entry(pt->session->evlist, evsel) {
  528. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  529. !evsel->attr.exclude_kernel)
  530. return false;
  531. }
  532. return true;
  533. }
  534. static bool intel_pt_return_compression(struct intel_pt *pt)
  535. {
  536. struct perf_evsel *evsel;
  537. u64 config;
  538. if (!pt->noretcomp_bit)
  539. return true;
  540. evlist__for_each_entry(pt->session->evlist, evsel) {
  541. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  542. (config & pt->noretcomp_bit))
  543. return false;
  544. }
  545. return true;
  546. }
  547. static bool intel_pt_branch_enable(struct intel_pt *pt)
  548. {
  549. struct perf_evsel *evsel;
  550. u64 config;
  551. evlist__for_each_entry(pt->session->evlist, evsel) {
  552. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  553. (config & 1) && !(config & 0x2000))
  554. return false;
  555. }
  556. return true;
  557. }
  558. static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
  559. {
  560. struct perf_evsel *evsel;
  561. unsigned int shift;
  562. u64 config;
  563. if (!pt->mtc_freq_bits)
  564. return 0;
  565. for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
  566. config >>= 1;
  567. evlist__for_each_entry(pt->session->evlist, evsel) {
  568. if (intel_pt_get_config(pt, &evsel->attr, &config))
  569. return (config & pt->mtc_freq_bits) >> shift;
  570. }
  571. return 0;
  572. }
  573. static bool intel_pt_timeless_decoding(struct intel_pt *pt)
  574. {
  575. struct perf_evsel *evsel;
  576. bool timeless_decoding = true;
  577. u64 config;
  578. if (!pt->tsc_bit || !pt->cap_user_time_zero)
  579. return true;
  580. evlist__for_each_entry(pt->session->evlist, evsel) {
  581. if (!(evsel->attr.sample_type & PERF_SAMPLE_TIME))
  582. return true;
  583. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  584. if (config & pt->tsc_bit)
  585. timeless_decoding = false;
  586. else
  587. return true;
  588. }
  589. }
  590. return timeless_decoding;
  591. }
  592. static bool intel_pt_tracing_kernel(struct intel_pt *pt)
  593. {
  594. struct perf_evsel *evsel;
  595. evlist__for_each_entry(pt->session->evlist, evsel) {
  596. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  597. !evsel->attr.exclude_kernel)
  598. return true;
  599. }
  600. return false;
  601. }
  602. static bool intel_pt_have_tsc(struct intel_pt *pt)
  603. {
  604. struct perf_evsel *evsel;
  605. bool have_tsc = false;
  606. u64 config;
  607. if (!pt->tsc_bit)
  608. return false;
  609. evlist__for_each_entry(pt->session->evlist, evsel) {
  610. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  611. if (config & pt->tsc_bit)
  612. have_tsc = true;
  613. else
  614. return false;
  615. }
  616. }
  617. return have_tsc;
  618. }
  619. static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
  620. {
  621. u64 quot, rem;
  622. quot = ns / pt->tc.time_mult;
  623. rem = ns % pt->tc.time_mult;
  624. return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
  625. pt->tc.time_mult;
  626. }
  627. static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
  628. unsigned int queue_nr)
  629. {
  630. struct intel_pt_params params = { .get_trace = 0, };
  631. struct perf_env *env = pt->machine->env;
  632. struct intel_pt_queue *ptq;
  633. ptq = zalloc(sizeof(struct intel_pt_queue));
  634. if (!ptq)
  635. return NULL;
  636. if (pt->synth_opts.callchain) {
  637. size_t sz = sizeof(struct ip_callchain);
  638. /* Add 1 to callchain_sz for callchain context */
  639. sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64);
  640. ptq->chain = zalloc(sz);
  641. if (!ptq->chain)
  642. goto out_free;
  643. }
  644. if (pt->synth_opts.last_branch) {
  645. size_t sz = sizeof(struct branch_stack);
  646. sz += pt->synth_opts.last_branch_sz *
  647. sizeof(struct branch_entry);
  648. ptq->last_branch = zalloc(sz);
  649. if (!ptq->last_branch)
  650. goto out_free;
  651. ptq->last_branch_rb = zalloc(sz);
  652. if (!ptq->last_branch_rb)
  653. goto out_free;
  654. }
  655. ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
  656. if (!ptq->event_buf)
  657. goto out_free;
  658. ptq->pt = pt;
  659. ptq->queue_nr = queue_nr;
  660. ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
  661. ptq->pid = -1;
  662. ptq->tid = -1;
  663. ptq->cpu = -1;
  664. ptq->next_tid = -1;
  665. params.get_trace = intel_pt_get_trace;
  666. params.walk_insn = intel_pt_walk_next_insn;
  667. params.data = ptq;
  668. params.return_compression = intel_pt_return_compression(pt);
  669. params.branch_enable = intel_pt_branch_enable(pt);
  670. params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
  671. params.mtc_period = intel_pt_mtc_period(pt);
  672. params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
  673. params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
  674. if (pt->filts.cnt > 0)
  675. params.pgd_ip = intel_pt_pgd_ip;
  676. if (pt->synth_opts.instructions) {
  677. if (pt->synth_opts.period) {
  678. switch (pt->synth_opts.period_type) {
  679. case PERF_ITRACE_PERIOD_INSTRUCTIONS:
  680. params.period_type =
  681. INTEL_PT_PERIOD_INSTRUCTIONS;
  682. params.period = pt->synth_opts.period;
  683. break;
  684. case PERF_ITRACE_PERIOD_TICKS:
  685. params.period_type = INTEL_PT_PERIOD_TICKS;
  686. params.period = pt->synth_opts.period;
  687. break;
  688. case PERF_ITRACE_PERIOD_NANOSECS:
  689. params.period_type = INTEL_PT_PERIOD_TICKS;
  690. params.period = intel_pt_ns_to_ticks(pt,
  691. pt->synth_opts.period);
  692. break;
  693. default:
  694. break;
  695. }
  696. }
  697. if (!params.period) {
  698. params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
  699. params.period = 1;
  700. }
  701. }
  702. if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
  703. params.flags |= INTEL_PT_FUP_WITH_NLIP;
  704. ptq->decoder = intel_pt_decoder_new(&params);
  705. if (!ptq->decoder)
  706. goto out_free;
  707. return ptq;
  708. out_free:
  709. zfree(&ptq->event_buf);
  710. zfree(&ptq->last_branch);
  711. zfree(&ptq->last_branch_rb);
  712. zfree(&ptq->chain);
  713. free(ptq);
  714. return NULL;
  715. }
  716. static void intel_pt_free_queue(void *priv)
  717. {
  718. struct intel_pt_queue *ptq = priv;
  719. if (!ptq)
  720. return;
  721. thread__zput(ptq->thread);
  722. intel_pt_decoder_free(ptq->decoder);
  723. zfree(&ptq->event_buf);
  724. zfree(&ptq->last_branch);
  725. zfree(&ptq->last_branch_rb);
  726. zfree(&ptq->chain);
  727. free(ptq);
  728. }
  729. static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
  730. struct auxtrace_queue *queue)
  731. {
  732. struct intel_pt_queue *ptq = queue->priv;
  733. if (queue->tid == -1 || pt->have_sched_switch) {
  734. ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
  735. thread__zput(ptq->thread);
  736. }
  737. if (!ptq->thread && ptq->tid != -1)
  738. ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
  739. if (ptq->thread) {
  740. ptq->pid = ptq->thread->pid_;
  741. if (queue->cpu == -1)
  742. ptq->cpu = ptq->thread->cpu;
  743. }
  744. }
  745. static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
  746. {
  747. if (ptq->state->flags & INTEL_PT_ABORT_TX) {
  748. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
  749. } else if (ptq->state->flags & INTEL_PT_ASYNC) {
  750. if (ptq->state->to_ip)
  751. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
  752. PERF_IP_FLAG_ASYNC |
  753. PERF_IP_FLAG_INTERRUPT;
  754. else
  755. ptq->flags = PERF_IP_FLAG_BRANCH |
  756. PERF_IP_FLAG_TRACE_END;
  757. ptq->insn_len = 0;
  758. } else {
  759. if (ptq->state->from_ip)
  760. ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
  761. else
  762. ptq->flags = PERF_IP_FLAG_BRANCH |
  763. PERF_IP_FLAG_TRACE_BEGIN;
  764. if (ptq->state->flags & INTEL_PT_IN_TX)
  765. ptq->flags |= PERF_IP_FLAG_IN_TX;
  766. ptq->insn_len = ptq->state->insn_len;
  767. memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
  768. }
  769. if (ptq->state->type & INTEL_PT_TRACE_BEGIN)
  770. ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN;
  771. if (ptq->state->type & INTEL_PT_TRACE_END)
  772. ptq->flags |= PERF_IP_FLAG_TRACE_END;
  773. }
  774. static int intel_pt_setup_queue(struct intel_pt *pt,
  775. struct auxtrace_queue *queue,
  776. unsigned int queue_nr)
  777. {
  778. struct intel_pt_queue *ptq = queue->priv;
  779. if (list_empty(&queue->head))
  780. return 0;
  781. if (!ptq) {
  782. ptq = intel_pt_alloc_queue(pt, queue_nr);
  783. if (!ptq)
  784. return -ENOMEM;
  785. queue->priv = ptq;
  786. if (queue->cpu != -1)
  787. ptq->cpu = queue->cpu;
  788. ptq->tid = queue->tid;
  789. if (pt->sampling_mode && !pt->snapshot_mode &&
  790. pt->timeless_decoding)
  791. ptq->step_through_buffers = true;
  792. ptq->sync_switch = pt->sync_switch;
  793. }
  794. if (!ptq->on_heap &&
  795. (!ptq->sync_switch ||
  796. ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
  797. const struct intel_pt_state *state;
  798. int ret;
  799. if (pt->timeless_decoding)
  800. return 0;
  801. intel_pt_log("queue %u getting timestamp\n", queue_nr);
  802. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  803. queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  804. while (1) {
  805. state = intel_pt_decode(ptq->decoder);
  806. if (state->err) {
  807. if (state->err == INTEL_PT_ERR_NODATA) {
  808. intel_pt_log("queue %u has no timestamp\n",
  809. queue_nr);
  810. return 0;
  811. }
  812. continue;
  813. }
  814. if (state->timestamp)
  815. break;
  816. }
  817. ptq->timestamp = state->timestamp;
  818. intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
  819. queue_nr, ptq->timestamp);
  820. ptq->state = state;
  821. ptq->have_sample = true;
  822. intel_pt_sample_flags(ptq);
  823. ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
  824. if (ret)
  825. return ret;
  826. ptq->on_heap = true;
  827. }
  828. return 0;
  829. }
  830. static int intel_pt_setup_queues(struct intel_pt *pt)
  831. {
  832. unsigned int i;
  833. int ret;
  834. for (i = 0; i < pt->queues.nr_queues; i++) {
  835. ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
  836. if (ret)
  837. return ret;
  838. }
  839. return 0;
  840. }
  841. static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq)
  842. {
  843. struct branch_stack *bs_src = ptq->last_branch_rb;
  844. struct branch_stack *bs_dst = ptq->last_branch;
  845. size_t nr = 0;
  846. bs_dst->nr = bs_src->nr;
  847. if (!bs_src->nr)
  848. return;
  849. nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos;
  850. memcpy(&bs_dst->entries[0],
  851. &bs_src->entries[ptq->last_branch_pos],
  852. sizeof(struct branch_entry) * nr);
  853. if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) {
  854. memcpy(&bs_dst->entries[nr],
  855. &bs_src->entries[0],
  856. sizeof(struct branch_entry) * ptq->last_branch_pos);
  857. }
  858. }
  859. static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq)
  860. {
  861. ptq->last_branch_pos = 0;
  862. ptq->last_branch_rb->nr = 0;
  863. }
  864. static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq)
  865. {
  866. const struct intel_pt_state *state = ptq->state;
  867. struct branch_stack *bs = ptq->last_branch_rb;
  868. struct branch_entry *be;
  869. if (!ptq->last_branch_pos)
  870. ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz;
  871. ptq->last_branch_pos -= 1;
  872. be = &bs->entries[ptq->last_branch_pos];
  873. be->from = state->from_ip;
  874. be->to = state->to_ip;
  875. be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX);
  876. be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX);
  877. /* No support for mispredict */
  878. be->flags.mispred = ptq->pt->mispred_all;
  879. if (bs->nr < ptq->pt->synth_opts.last_branch_sz)
  880. bs->nr += 1;
  881. }
  882. static inline bool intel_pt_skip_event(struct intel_pt *pt)
  883. {
  884. return pt->synth_opts.initial_skip &&
  885. pt->num_events++ < pt->synth_opts.initial_skip;
  886. }
  887. static void intel_pt_prep_b_sample(struct intel_pt *pt,
  888. struct intel_pt_queue *ptq,
  889. union perf_event *event,
  890. struct perf_sample *sample)
  891. {
  892. if (!pt->timeless_decoding)
  893. sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  894. sample->ip = ptq->state->from_ip;
  895. sample->cpumode = intel_pt_cpumode(pt, sample->ip);
  896. sample->pid = ptq->pid;
  897. sample->tid = ptq->tid;
  898. sample->addr = ptq->state->to_ip;
  899. sample->period = 1;
  900. sample->cpu = ptq->cpu;
  901. sample->flags = ptq->flags;
  902. sample->insn_len = ptq->insn_len;
  903. memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
  904. event->sample.header.type = PERF_RECORD_SAMPLE;
  905. event->sample.header.misc = sample->cpumode;
  906. event->sample.header.size = sizeof(struct perf_event_header);
  907. }
  908. static int intel_pt_inject_event(union perf_event *event,
  909. struct perf_sample *sample, u64 type)
  910. {
  911. event->header.size = perf_event__sample_event_size(sample, type, 0);
  912. return perf_event__synthesize_sample(event, type, 0, sample);
  913. }
  914. static inline int intel_pt_opt_inject(struct intel_pt *pt,
  915. union perf_event *event,
  916. struct perf_sample *sample, u64 type)
  917. {
  918. if (!pt->synth_opts.inject)
  919. return 0;
  920. return intel_pt_inject_event(event, sample, type);
  921. }
  922. static int intel_pt_deliver_synth_b_event(struct intel_pt *pt,
  923. union perf_event *event,
  924. struct perf_sample *sample, u64 type)
  925. {
  926. int ret;
  927. ret = intel_pt_opt_inject(pt, event, sample, type);
  928. if (ret)
  929. return ret;
  930. ret = perf_session__deliver_synth_event(pt->session, event, sample);
  931. if (ret)
  932. pr_err("Intel PT: failed to deliver event, error %d\n", ret);
  933. return ret;
  934. }
  935. static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
  936. {
  937. struct intel_pt *pt = ptq->pt;
  938. union perf_event *event = ptq->event_buf;
  939. struct perf_sample sample = { .ip = 0, };
  940. struct dummy_branch_stack {
  941. u64 nr;
  942. struct branch_entry entries;
  943. } dummy_bs;
  944. if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
  945. return 0;
  946. if (intel_pt_skip_event(pt))
  947. return 0;
  948. intel_pt_prep_b_sample(pt, ptq, event, &sample);
  949. sample.id = ptq->pt->branches_id;
  950. sample.stream_id = ptq->pt->branches_id;
  951. /*
  952. * perf report cannot handle events without a branch stack when using
  953. * SORT_MODE__BRANCH so make a dummy one.
  954. */
  955. if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
  956. dummy_bs = (struct dummy_branch_stack){
  957. .nr = 1,
  958. .entries = {
  959. .from = sample.ip,
  960. .to = sample.addr,
  961. },
  962. };
  963. sample.branch_stack = (struct branch_stack *)&dummy_bs;
  964. }
  965. return intel_pt_deliver_synth_b_event(pt, event, &sample,
  966. pt->branches_sample_type);
  967. }
  968. static void intel_pt_prep_sample(struct intel_pt *pt,
  969. struct intel_pt_queue *ptq,
  970. union perf_event *event,
  971. struct perf_sample *sample)
  972. {
  973. intel_pt_prep_b_sample(pt, ptq, event, sample);
  974. if (pt->synth_opts.callchain) {
  975. thread_stack__sample(ptq->thread, ptq->chain,
  976. pt->synth_opts.callchain_sz + 1,
  977. sample->ip, pt->kernel_start);
  978. sample->callchain = ptq->chain;
  979. }
  980. if (pt->synth_opts.last_branch) {
  981. intel_pt_copy_last_branch_rb(ptq);
  982. sample->branch_stack = ptq->last_branch;
  983. }
  984. }
  985. static inline int intel_pt_deliver_synth_event(struct intel_pt *pt,
  986. struct intel_pt_queue *ptq,
  987. union perf_event *event,
  988. struct perf_sample *sample,
  989. u64 type)
  990. {
  991. int ret;
  992. ret = intel_pt_deliver_synth_b_event(pt, event, sample, type);
  993. if (pt->synth_opts.last_branch)
  994. intel_pt_reset_last_branch_rb(ptq);
  995. return ret;
  996. }
  997. static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
  998. {
  999. struct intel_pt *pt = ptq->pt;
  1000. union perf_event *event = ptq->event_buf;
  1001. struct perf_sample sample = { .ip = 0, };
  1002. if (intel_pt_skip_event(pt))
  1003. return 0;
  1004. intel_pt_prep_sample(pt, ptq, event, &sample);
  1005. sample.id = ptq->pt->instructions_id;
  1006. sample.stream_id = ptq->pt->instructions_id;
  1007. sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
  1008. ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
  1009. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1010. pt->instructions_sample_type);
  1011. }
  1012. static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
  1013. {
  1014. struct intel_pt *pt = ptq->pt;
  1015. union perf_event *event = ptq->event_buf;
  1016. struct perf_sample sample = { .ip = 0, };
  1017. if (intel_pt_skip_event(pt))
  1018. return 0;
  1019. intel_pt_prep_sample(pt, ptq, event, &sample);
  1020. sample.id = ptq->pt->transactions_id;
  1021. sample.stream_id = ptq->pt->transactions_id;
  1022. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1023. pt->transactions_sample_type);
  1024. }
  1025. static void intel_pt_prep_p_sample(struct intel_pt *pt,
  1026. struct intel_pt_queue *ptq,
  1027. union perf_event *event,
  1028. struct perf_sample *sample)
  1029. {
  1030. intel_pt_prep_sample(pt, ptq, event, sample);
  1031. /*
  1032. * Zero IP is used to mean "trace start" but that is not the case for
  1033. * power or PTWRITE events with no IP, so clear the flags.
  1034. */
  1035. if (!sample->ip)
  1036. sample->flags = 0;
  1037. }
  1038. static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
  1039. {
  1040. struct intel_pt *pt = ptq->pt;
  1041. union perf_event *event = ptq->event_buf;
  1042. struct perf_sample sample = { .ip = 0, };
  1043. struct perf_synth_intel_ptwrite raw;
  1044. if (intel_pt_skip_event(pt))
  1045. return 0;
  1046. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1047. sample.id = ptq->pt->ptwrites_id;
  1048. sample.stream_id = ptq->pt->ptwrites_id;
  1049. raw.flags = 0;
  1050. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1051. raw.payload = cpu_to_le64(ptq->state->ptw_payload);
  1052. sample.raw_size = perf_synth__raw_size(raw);
  1053. sample.raw_data = perf_synth__raw_data(&raw);
  1054. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1055. pt->ptwrites_sample_type);
  1056. }
  1057. static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
  1058. {
  1059. struct intel_pt *pt = ptq->pt;
  1060. union perf_event *event = ptq->event_buf;
  1061. struct perf_sample sample = { .ip = 0, };
  1062. struct perf_synth_intel_cbr raw;
  1063. u32 flags;
  1064. if (intel_pt_skip_event(pt))
  1065. return 0;
  1066. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1067. sample.id = ptq->pt->cbr_id;
  1068. sample.stream_id = ptq->pt->cbr_id;
  1069. flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
  1070. raw.flags = cpu_to_le32(flags);
  1071. raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
  1072. raw.reserved3 = 0;
  1073. sample.raw_size = perf_synth__raw_size(raw);
  1074. sample.raw_data = perf_synth__raw_data(&raw);
  1075. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1076. pt->pwr_events_sample_type);
  1077. }
  1078. static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
  1079. {
  1080. struct intel_pt *pt = ptq->pt;
  1081. union perf_event *event = ptq->event_buf;
  1082. struct perf_sample sample = { .ip = 0, };
  1083. struct perf_synth_intel_mwait raw;
  1084. if (intel_pt_skip_event(pt))
  1085. return 0;
  1086. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1087. sample.id = ptq->pt->mwait_id;
  1088. sample.stream_id = ptq->pt->mwait_id;
  1089. raw.reserved = 0;
  1090. raw.payload = cpu_to_le64(ptq->state->mwait_payload);
  1091. sample.raw_size = perf_synth__raw_size(raw);
  1092. sample.raw_data = perf_synth__raw_data(&raw);
  1093. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1094. pt->pwr_events_sample_type);
  1095. }
  1096. static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
  1097. {
  1098. struct intel_pt *pt = ptq->pt;
  1099. union perf_event *event = ptq->event_buf;
  1100. struct perf_sample sample = { .ip = 0, };
  1101. struct perf_synth_intel_pwre raw;
  1102. if (intel_pt_skip_event(pt))
  1103. return 0;
  1104. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1105. sample.id = ptq->pt->pwre_id;
  1106. sample.stream_id = ptq->pt->pwre_id;
  1107. raw.reserved = 0;
  1108. raw.payload = cpu_to_le64(ptq->state->pwre_payload);
  1109. sample.raw_size = perf_synth__raw_size(raw);
  1110. sample.raw_data = perf_synth__raw_data(&raw);
  1111. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1112. pt->pwr_events_sample_type);
  1113. }
  1114. static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
  1115. {
  1116. struct intel_pt *pt = ptq->pt;
  1117. union perf_event *event = ptq->event_buf;
  1118. struct perf_sample sample = { .ip = 0, };
  1119. struct perf_synth_intel_exstop raw;
  1120. if (intel_pt_skip_event(pt))
  1121. return 0;
  1122. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1123. sample.id = ptq->pt->exstop_id;
  1124. sample.stream_id = ptq->pt->exstop_id;
  1125. raw.flags = 0;
  1126. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1127. sample.raw_size = perf_synth__raw_size(raw);
  1128. sample.raw_data = perf_synth__raw_data(&raw);
  1129. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1130. pt->pwr_events_sample_type);
  1131. }
  1132. static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
  1133. {
  1134. struct intel_pt *pt = ptq->pt;
  1135. union perf_event *event = ptq->event_buf;
  1136. struct perf_sample sample = { .ip = 0, };
  1137. struct perf_synth_intel_pwrx raw;
  1138. if (intel_pt_skip_event(pt))
  1139. return 0;
  1140. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1141. sample.id = ptq->pt->pwrx_id;
  1142. sample.stream_id = ptq->pt->pwrx_id;
  1143. raw.reserved = 0;
  1144. raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
  1145. sample.raw_size = perf_synth__raw_size(raw);
  1146. sample.raw_data = perf_synth__raw_data(&raw);
  1147. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1148. pt->pwr_events_sample_type);
  1149. }
  1150. static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
  1151. pid_t pid, pid_t tid, u64 ip)
  1152. {
  1153. union perf_event event;
  1154. char msg[MAX_AUXTRACE_ERROR_MSG];
  1155. int err;
  1156. intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
  1157. auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
  1158. code, cpu, pid, tid, ip, msg);
  1159. err = perf_session__deliver_synth_event(pt->session, &event, NULL);
  1160. if (err)
  1161. pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
  1162. err);
  1163. return err;
  1164. }
  1165. static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
  1166. {
  1167. struct auxtrace_queue *queue;
  1168. pid_t tid = ptq->next_tid;
  1169. int err;
  1170. if (tid == -1)
  1171. return 0;
  1172. intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
  1173. err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
  1174. queue = &pt->queues.queue_array[ptq->queue_nr];
  1175. intel_pt_set_pid_tid_cpu(pt, queue);
  1176. ptq->next_tid = -1;
  1177. return err;
  1178. }
  1179. static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
  1180. {
  1181. struct intel_pt *pt = ptq->pt;
  1182. return ip == pt->switch_ip &&
  1183. (ptq->flags & PERF_IP_FLAG_BRANCH) &&
  1184. !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
  1185. PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
  1186. }
  1187. #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
  1188. INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT | \
  1189. INTEL_PT_CBR_CHG)
  1190. static int intel_pt_sample(struct intel_pt_queue *ptq)
  1191. {
  1192. const struct intel_pt_state *state = ptq->state;
  1193. struct intel_pt *pt = ptq->pt;
  1194. int err;
  1195. if (!ptq->have_sample)
  1196. return 0;
  1197. ptq->have_sample = false;
  1198. if (pt->sample_pwr_events && (state->type & INTEL_PT_PWR_EVT)) {
  1199. if (state->type & INTEL_PT_CBR_CHG) {
  1200. err = intel_pt_synth_cbr_sample(ptq);
  1201. if (err)
  1202. return err;
  1203. }
  1204. if (state->type & INTEL_PT_MWAIT_OP) {
  1205. err = intel_pt_synth_mwait_sample(ptq);
  1206. if (err)
  1207. return err;
  1208. }
  1209. if (state->type & INTEL_PT_PWR_ENTRY) {
  1210. err = intel_pt_synth_pwre_sample(ptq);
  1211. if (err)
  1212. return err;
  1213. }
  1214. if (state->type & INTEL_PT_EX_STOP) {
  1215. err = intel_pt_synth_exstop_sample(ptq);
  1216. if (err)
  1217. return err;
  1218. }
  1219. if (state->type & INTEL_PT_PWR_EXIT) {
  1220. err = intel_pt_synth_pwrx_sample(ptq);
  1221. if (err)
  1222. return err;
  1223. }
  1224. }
  1225. if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
  1226. err = intel_pt_synth_instruction_sample(ptq);
  1227. if (err)
  1228. return err;
  1229. }
  1230. if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
  1231. err = intel_pt_synth_transaction_sample(ptq);
  1232. if (err)
  1233. return err;
  1234. }
  1235. if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
  1236. err = intel_pt_synth_ptwrite_sample(ptq);
  1237. if (err)
  1238. return err;
  1239. }
  1240. if (!(state->type & INTEL_PT_BRANCH))
  1241. return 0;
  1242. if (pt->synth_opts.callchain || pt->synth_opts.thread_stack)
  1243. thread_stack__event(ptq->thread, ptq->flags, state->from_ip,
  1244. state->to_ip, ptq->insn_len,
  1245. state->trace_nr);
  1246. else
  1247. thread_stack__set_trace_nr(ptq->thread, state->trace_nr);
  1248. if (pt->sample_branches) {
  1249. err = intel_pt_synth_branch_sample(ptq);
  1250. if (err)
  1251. return err;
  1252. }
  1253. if (pt->synth_opts.last_branch)
  1254. intel_pt_update_last_branch_rb(ptq);
  1255. if (!ptq->sync_switch)
  1256. return 0;
  1257. if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
  1258. switch (ptq->switch_state) {
  1259. case INTEL_PT_SS_NOT_TRACING:
  1260. case INTEL_PT_SS_UNKNOWN:
  1261. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1262. err = intel_pt_next_tid(pt, ptq);
  1263. if (err)
  1264. return err;
  1265. ptq->switch_state = INTEL_PT_SS_TRACING;
  1266. break;
  1267. default:
  1268. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
  1269. return 1;
  1270. }
  1271. } else if (!state->to_ip) {
  1272. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1273. } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
  1274. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1275. } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1276. state->to_ip == pt->ptss_ip &&
  1277. (ptq->flags & PERF_IP_FLAG_CALL)) {
  1278. ptq->switch_state = INTEL_PT_SS_TRACING;
  1279. }
  1280. return 0;
  1281. }
  1282. static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
  1283. {
  1284. struct machine *machine = pt->machine;
  1285. struct map *map;
  1286. struct symbol *sym, *start;
  1287. u64 ip, switch_ip = 0;
  1288. const char *ptss;
  1289. if (ptss_ip)
  1290. *ptss_ip = 0;
  1291. map = machine__kernel_map(machine);
  1292. if (!map)
  1293. return 0;
  1294. if (map__load(map))
  1295. return 0;
  1296. start = dso__first_symbol(map->dso);
  1297. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1298. if (sym->binding == STB_GLOBAL &&
  1299. !strcmp(sym->name, "__switch_to")) {
  1300. ip = map->unmap_ip(map, sym->start);
  1301. if (ip >= map->start && ip < map->end) {
  1302. switch_ip = ip;
  1303. break;
  1304. }
  1305. }
  1306. }
  1307. if (!switch_ip || !ptss_ip)
  1308. return 0;
  1309. if (pt->have_sched_switch == 1)
  1310. ptss = "perf_trace_sched_switch";
  1311. else
  1312. ptss = "__perf_event_task_sched_out";
  1313. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1314. if (!strcmp(sym->name, ptss)) {
  1315. ip = map->unmap_ip(map, sym->start);
  1316. if (ip >= map->start && ip < map->end) {
  1317. *ptss_ip = ip;
  1318. break;
  1319. }
  1320. }
  1321. }
  1322. return switch_ip;
  1323. }
  1324. static void intel_pt_enable_sync_switch(struct intel_pt *pt)
  1325. {
  1326. unsigned int i;
  1327. pt->sync_switch = true;
  1328. for (i = 0; i < pt->queues.nr_queues; i++) {
  1329. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1330. struct intel_pt_queue *ptq = queue->priv;
  1331. if (ptq)
  1332. ptq->sync_switch = true;
  1333. }
  1334. }
  1335. static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
  1336. {
  1337. const struct intel_pt_state *state = ptq->state;
  1338. struct intel_pt *pt = ptq->pt;
  1339. int err;
  1340. if (!pt->kernel_start) {
  1341. pt->kernel_start = machine__kernel_start(pt->machine);
  1342. if (pt->per_cpu_mmaps &&
  1343. (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
  1344. !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
  1345. !pt->sampling_mode) {
  1346. pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
  1347. if (pt->switch_ip) {
  1348. intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
  1349. pt->switch_ip, pt->ptss_ip);
  1350. intel_pt_enable_sync_switch(pt);
  1351. }
  1352. }
  1353. }
  1354. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1355. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1356. while (1) {
  1357. err = intel_pt_sample(ptq);
  1358. if (err)
  1359. return err;
  1360. state = intel_pt_decode(ptq->decoder);
  1361. if (state->err) {
  1362. if (state->err == INTEL_PT_ERR_NODATA)
  1363. return 1;
  1364. if (ptq->sync_switch &&
  1365. state->from_ip >= pt->kernel_start) {
  1366. ptq->sync_switch = false;
  1367. intel_pt_next_tid(pt, ptq);
  1368. }
  1369. if (pt->synth_opts.errors) {
  1370. err = intel_pt_synth_error(pt, state->err,
  1371. ptq->cpu, ptq->pid,
  1372. ptq->tid,
  1373. state->from_ip);
  1374. if (err)
  1375. return err;
  1376. }
  1377. continue;
  1378. }
  1379. ptq->state = state;
  1380. ptq->have_sample = true;
  1381. intel_pt_sample_flags(ptq);
  1382. /* Use estimated TSC upon return to user space */
  1383. if (pt->est_tsc &&
  1384. (state->from_ip >= pt->kernel_start || !state->from_ip) &&
  1385. state->to_ip && state->to_ip < pt->kernel_start) {
  1386. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1387. state->timestamp, state->est_timestamp);
  1388. ptq->timestamp = state->est_timestamp;
  1389. /* Use estimated TSC in unknown switch state */
  1390. } else if (ptq->sync_switch &&
  1391. ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1392. intel_pt_is_switch_ip(ptq, state->to_ip) &&
  1393. ptq->next_tid == -1) {
  1394. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1395. state->timestamp, state->est_timestamp);
  1396. ptq->timestamp = state->est_timestamp;
  1397. } else if (state->timestamp > ptq->timestamp) {
  1398. ptq->timestamp = state->timestamp;
  1399. }
  1400. if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
  1401. *timestamp = ptq->timestamp;
  1402. return 0;
  1403. }
  1404. }
  1405. return 0;
  1406. }
  1407. static inline int intel_pt_update_queues(struct intel_pt *pt)
  1408. {
  1409. if (pt->queues.new_data) {
  1410. pt->queues.new_data = false;
  1411. return intel_pt_setup_queues(pt);
  1412. }
  1413. return 0;
  1414. }
  1415. static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
  1416. {
  1417. unsigned int queue_nr;
  1418. u64 ts;
  1419. int ret;
  1420. while (1) {
  1421. struct auxtrace_queue *queue;
  1422. struct intel_pt_queue *ptq;
  1423. if (!pt->heap.heap_cnt)
  1424. return 0;
  1425. if (pt->heap.heap_array[0].ordinal >= timestamp)
  1426. return 0;
  1427. queue_nr = pt->heap.heap_array[0].queue_nr;
  1428. queue = &pt->queues.queue_array[queue_nr];
  1429. ptq = queue->priv;
  1430. intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
  1431. queue_nr, pt->heap.heap_array[0].ordinal,
  1432. timestamp);
  1433. auxtrace_heap__pop(&pt->heap);
  1434. if (pt->heap.heap_cnt) {
  1435. ts = pt->heap.heap_array[0].ordinal + 1;
  1436. if (ts > timestamp)
  1437. ts = timestamp;
  1438. } else {
  1439. ts = timestamp;
  1440. }
  1441. intel_pt_set_pid_tid_cpu(pt, queue);
  1442. ret = intel_pt_run_decoder(ptq, &ts);
  1443. if (ret < 0) {
  1444. auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1445. return ret;
  1446. }
  1447. if (!ret) {
  1448. ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1449. if (ret < 0)
  1450. return ret;
  1451. } else {
  1452. ptq->on_heap = false;
  1453. }
  1454. }
  1455. return 0;
  1456. }
  1457. static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
  1458. u64 time_)
  1459. {
  1460. struct auxtrace_queues *queues = &pt->queues;
  1461. unsigned int i;
  1462. u64 ts = 0;
  1463. for (i = 0; i < queues->nr_queues; i++) {
  1464. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1465. struct intel_pt_queue *ptq = queue->priv;
  1466. if (ptq && (tid == -1 || ptq->tid == tid)) {
  1467. ptq->time = time_;
  1468. intel_pt_set_pid_tid_cpu(pt, queue);
  1469. intel_pt_run_decoder(ptq, &ts);
  1470. }
  1471. }
  1472. return 0;
  1473. }
  1474. static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
  1475. {
  1476. return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
  1477. sample->pid, sample->tid, 0);
  1478. }
  1479. static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
  1480. {
  1481. unsigned i, j;
  1482. if (cpu < 0 || !pt->queues.nr_queues)
  1483. return NULL;
  1484. if ((unsigned)cpu >= pt->queues.nr_queues)
  1485. i = pt->queues.nr_queues - 1;
  1486. else
  1487. i = cpu;
  1488. if (pt->queues.queue_array[i].cpu == cpu)
  1489. return pt->queues.queue_array[i].priv;
  1490. for (j = 0; i > 0; j++) {
  1491. if (pt->queues.queue_array[--i].cpu == cpu)
  1492. return pt->queues.queue_array[i].priv;
  1493. }
  1494. for (; j < pt->queues.nr_queues; j++) {
  1495. if (pt->queues.queue_array[j].cpu == cpu)
  1496. return pt->queues.queue_array[j].priv;
  1497. }
  1498. return NULL;
  1499. }
  1500. static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
  1501. u64 timestamp)
  1502. {
  1503. struct intel_pt_queue *ptq;
  1504. int err;
  1505. if (!pt->sync_switch)
  1506. return 1;
  1507. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  1508. if (!ptq || !ptq->sync_switch)
  1509. return 1;
  1510. switch (ptq->switch_state) {
  1511. case INTEL_PT_SS_NOT_TRACING:
  1512. ptq->next_tid = -1;
  1513. break;
  1514. case INTEL_PT_SS_UNKNOWN:
  1515. case INTEL_PT_SS_TRACING:
  1516. ptq->next_tid = tid;
  1517. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
  1518. return 0;
  1519. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  1520. if (!ptq->on_heap) {
  1521. ptq->timestamp = perf_time_to_tsc(timestamp,
  1522. &pt->tc);
  1523. err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
  1524. ptq->timestamp);
  1525. if (err)
  1526. return err;
  1527. ptq->on_heap = true;
  1528. }
  1529. ptq->switch_state = INTEL_PT_SS_TRACING;
  1530. break;
  1531. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1532. ptq->next_tid = tid;
  1533. intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
  1534. break;
  1535. default:
  1536. break;
  1537. }
  1538. return 1;
  1539. }
  1540. static int intel_pt_process_switch(struct intel_pt *pt,
  1541. struct perf_sample *sample)
  1542. {
  1543. struct perf_evsel *evsel;
  1544. pid_t tid;
  1545. int cpu, ret;
  1546. evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
  1547. if (evsel != pt->switch_evsel)
  1548. return 0;
  1549. tid = perf_evsel__intval(evsel, sample, "next_pid");
  1550. cpu = sample->cpu;
  1551. intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1552. cpu, tid, sample->time, perf_time_to_tsc(sample->time,
  1553. &pt->tc));
  1554. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1555. if (ret <= 0)
  1556. return ret;
  1557. return machine__set_current_tid(pt->machine, cpu, -1, tid);
  1558. }
  1559. static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
  1560. struct perf_sample *sample)
  1561. {
  1562. bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
  1563. pid_t pid, tid;
  1564. int cpu, ret;
  1565. cpu = sample->cpu;
  1566. if (pt->have_sched_switch == 3) {
  1567. if (!out)
  1568. return 0;
  1569. if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
  1570. pr_err("Expecting CPU-wide context switch event\n");
  1571. return -EINVAL;
  1572. }
  1573. pid = event->context_switch.next_prev_pid;
  1574. tid = event->context_switch.next_prev_tid;
  1575. } else {
  1576. if (out)
  1577. return 0;
  1578. pid = sample->pid;
  1579. tid = sample->tid;
  1580. }
  1581. if (tid == -1) {
  1582. pr_err("context_switch event has no tid\n");
  1583. return -EINVAL;
  1584. }
  1585. intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1586. cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time,
  1587. &pt->tc));
  1588. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1589. if (ret <= 0)
  1590. return ret;
  1591. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  1592. }
  1593. static int intel_pt_process_itrace_start(struct intel_pt *pt,
  1594. union perf_event *event,
  1595. struct perf_sample *sample)
  1596. {
  1597. if (!pt->per_cpu_mmaps)
  1598. return 0;
  1599. intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1600. sample->cpu, event->itrace_start.pid,
  1601. event->itrace_start.tid, sample->time,
  1602. perf_time_to_tsc(sample->time, &pt->tc));
  1603. return machine__set_current_tid(pt->machine, sample->cpu,
  1604. event->itrace_start.pid,
  1605. event->itrace_start.tid);
  1606. }
  1607. static int intel_pt_process_event(struct perf_session *session,
  1608. union perf_event *event,
  1609. struct perf_sample *sample,
  1610. struct perf_tool *tool)
  1611. {
  1612. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1613. auxtrace);
  1614. u64 timestamp;
  1615. int err = 0;
  1616. if (dump_trace)
  1617. return 0;
  1618. if (!tool->ordered_events) {
  1619. pr_err("Intel Processor Trace requires ordered events\n");
  1620. return -EINVAL;
  1621. }
  1622. if (sample->time && sample->time != (u64)-1)
  1623. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  1624. else
  1625. timestamp = 0;
  1626. if (timestamp || pt->timeless_decoding) {
  1627. err = intel_pt_update_queues(pt);
  1628. if (err)
  1629. return err;
  1630. }
  1631. if (pt->timeless_decoding) {
  1632. if (event->header.type == PERF_RECORD_EXIT) {
  1633. err = intel_pt_process_timeless_queues(pt,
  1634. event->fork.tid,
  1635. sample->time);
  1636. }
  1637. } else if (timestamp) {
  1638. err = intel_pt_process_queues(pt, timestamp);
  1639. }
  1640. if (err)
  1641. return err;
  1642. if (event->header.type == PERF_RECORD_AUX &&
  1643. (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
  1644. pt->synth_opts.errors) {
  1645. err = intel_pt_lost(pt, sample);
  1646. if (err)
  1647. return err;
  1648. }
  1649. if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
  1650. err = intel_pt_process_switch(pt, sample);
  1651. else if (event->header.type == PERF_RECORD_ITRACE_START)
  1652. err = intel_pt_process_itrace_start(pt, event, sample);
  1653. else if (event->header.type == PERF_RECORD_SWITCH ||
  1654. event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
  1655. err = intel_pt_context_switch(pt, event, sample);
  1656. intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ",
  1657. event->header.type, sample->cpu, sample->time, timestamp);
  1658. intel_pt_log_event(event);
  1659. return err;
  1660. }
  1661. static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
  1662. {
  1663. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1664. auxtrace);
  1665. int ret;
  1666. if (dump_trace)
  1667. return 0;
  1668. if (!tool->ordered_events)
  1669. return -EINVAL;
  1670. ret = intel_pt_update_queues(pt);
  1671. if (ret < 0)
  1672. return ret;
  1673. if (pt->timeless_decoding)
  1674. return intel_pt_process_timeless_queues(pt, -1,
  1675. MAX_TIMESTAMP - 1);
  1676. return intel_pt_process_queues(pt, MAX_TIMESTAMP);
  1677. }
  1678. static void intel_pt_free_events(struct perf_session *session)
  1679. {
  1680. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1681. auxtrace);
  1682. struct auxtrace_queues *queues = &pt->queues;
  1683. unsigned int i;
  1684. for (i = 0; i < queues->nr_queues; i++) {
  1685. intel_pt_free_queue(queues->queue_array[i].priv);
  1686. queues->queue_array[i].priv = NULL;
  1687. }
  1688. intel_pt_log_disable();
  1689. auxtrace_queues__free(queues);
  1690. }
  1691. static void intel_pt_free(struct perf_session *session)
  1692. {
  1693. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1694. auxtrace);
  1695. auxtrace_heap__free(&pt->heap);
  1696. intel_pt_free_events(session);
  1697. session->auxtrace = NULL;
  1698. thread__put(pt->unknown_thread);
  1699. addr_filters__exit(&pt->filts);
  1700. zfree(&pt->filter);
  1701. free(pt);
  1702. }
  1703. static int intel_pt_process_auxtrace_event(struct perf_session *session,
  1704. union perf_event *event,
  1705. struct perf_tool *tool __maybe_unused)
  1706. {
  1707. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1708. auxtrace);
  1709. if (!pt->data_queued) {
  1710. struct auxtrace_buffer *buffer;
  1711. off_t data_offset;
  1712. int fd = perf_data__fd(session->data);
  1713. int err;
  1714. if (perf_data__is_pipe(session->data)) {
  1715. data_offset = 0;
  1716. } else {
  1717. data_offset = lseek(fd, 0, SEEK_CUR);
  1718. if (data_offset == -1)
  1719. return -errno;
  1720. }
  1721. err = auxtrace_queues__add_event(&pt->queues, session, event,
  1722. data_offset, &buffer);
  1723. if (err)
  1724. return err;
  1725. /* Dump here now we have copied a piped trace out of the pipe */
  1726. if (dump_trace) {
  1727. if (auxtrace_buffer__get_data(buffer, fd)) {
  1728. intel_pt_dump_event(pt, buffer->data,
  1729. buffer->size);
  1730. auxtrace_buffer__put_data(buffer);
  1731. }
  1732. }
  1733. }
  1734. return 0;
  1735. }
  1736. struct intel_pt_synth {
  1737. struct perf_tool dummy_tool;
  1738. struct perf_session *session;
  1739. };
  1740. static int intel_pt_event_synth(struct perf_tool *tool,
  1741. union perf_event *event,
  1742. struct perf_sample *sample __maybe_unused,
  1743. struct machine *machine __maybe_unused)
  1744. {
  1745. struct intel_pt_synth *intel_pt_synth =
  1746. container_of(tool, struct intel_pt_synth, dummy_tool);
  1747. return perf_session__deliver_synth_event(intel_pt_synth->session, event,
  1748. NULL);
  1749. }
  1750. static int intel_pt_synth_event(struct perf_session *session, const char *name,
  1751. struct perf_event_attr *attr, u64 id)
  1752. {
  1753. struct intel_pt_synth intel_pt_synth;
  1754. int err;
  1755. pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1756. name, id, (u64)attr->sample_type);
  1757. memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
  1758. intel_pt_synth.session = session;
  1759. err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
  1760. &id, intel_pt_event_synth);
  1761. if (err)
  1762. pr_err("%s: failed to synthesize '%s' event type\n",
  1763. __func__, name);
  1764. return err;
  1765. }
  1766. static void intel_pt_set_event_name(struct perf_evlist *evlist, u64 id,
  1767. const char *name)
  1768. {
  1769. struct perf_evsel *evsel;
  1770. evlist__for_each_entry(evlist, evsel) {
  1771. if (evsel->id && evsel->id[0] == id) {
  1772. if (evsel->name)
  1773. zfree(&evsel->name);
  1774. evsel->name = strdup(name);
  1775. break;
  1776. }
  1777. }
  1778. }
  1779. static struct perf_evsel *intel_pt_evsel(struct intel_pt *pt,
  1780. struct perf_evlist *evlist)
  1781. {
  1782. struct perf_evsel *evsel;
  1783. evlist__for_each_entry(evlist, evsel) {
  1784. if (evsel->attr.type == pt->pmu_type && evsel->ids)
  1785. return evsel;
  1786. }
  1787. return NULL;
  1788. }
  1789. static int intel_pt_synth_events(struct intel_pt *pt,
  1790. struct perf_session *session)
  1791. {
  1792. struct perf_evlist *evlist = session->evlist;
  1793. struct perf_evsel *evsel = intel_pt_evsel(pt, evlist);
  1794. struct perf_event_attr attr;
  1795. u64 id;
  1796. int err;
  1797. if (!evsel) {
  1798. pr_debug("There are no selected events with Intel Processor Trace data\n");
  1799. return 0;
  1800. }
  1801. memset(&attr, 0, sizeof(struct perf_event_attr));
  1802. attr.size = sizeof(struct perf_event_attr);
  1803. attr.type = PERF_TYPE_HARDWARE;
  1804. attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
  1805. attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
  1806. PERF_SAMPLE_PERIOD;
  1807. if (pt->timeless_decoding)
  1808. attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
  1809. else
  1810. attr.sample_type |= PERF_SAMPLE_TIME;
  1811. if (!pt->per_cpu_mmaps)
  1812. attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
  1813. attr.exclude_user = evsel->attr.exclude_user;
  1814. attr.exclude_kernel = evsel->attr.exclude_kernel;
  1815. attr.exclude_hv = evsel->attr.exclude_hv;
  1816. attr.exclude_host = evsel->attr.exclude_host;
  1817. attr.exclude_guest = evsel->attr.exclude_guest;
  1818. attr.sample_id_all = evsel->attr.sample_id_all;
  1819. attr.read_format = evsel->attr.read_format;
  1820. id = evsel->id[0] + 1000000000;
  1821. if (!id)
  1822. id = 1;
  1823. if (pt->synth_opts.branches) {
  1824. attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
  1825. attr.sample_period = 1;
  1826. attr.sample_type |= PERF_SAMPLE_ADDR;
  1827. err = intel_pt_synth_event(session, "branches", &attr, id);
  1828. if (err)
  1829. return err;
  1830. pt->sample_branches = true;
  1831. pt->branches_sample_type = attr.sample_type;
  1832. pt->branches_id = id;
  1833. id += 1;
  1834. attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
  1835. }
  1836. if (pt->synth_opts.callchain)
  1837. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1838. if (pt->synth_opts.last_branch)
  1839. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1840. if (pt->synth_opts.instructions) {
  1841. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1842. if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
  1843. attr.sample_period =
  1844. intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
  1845. else
  1846. attr.sample_period = pt->synth_opts.period;
  1847. err = intel_pt_synth_event(session, "instructions", &attr, id);
  1848. if (err)
  1849. return err;
  1850. pt->sample_instructions = true;
  1851. pt->instructions_sample_type = attr.sample_type;
  1852. pt->instructions_id = id;
  1853. id += 1;
  1854. }
  1855. attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
  1856. attr.sample_period = 1;
  1857. if (pt->synth_opts.transactions) {
  1858. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1859. err = intel_pt_synth_event(session, "transactions", &attr, id);
  1860. if (err)
  1861. return err;
  1862. pt->sample_transactions = true;
  1863. pt->transactions_sample_type = attr.sample_type;
  1864. pt->transactions_id = id;
  1865. intel_pt_set_event_name(evlist, id, "transactions");
  1866. id += 1;
  1867. }
  1868. attr.type = PERF_TYPE_SYNTH;
  1869. attr.sample_type |= PERF_SAMPLE_RAW;
  1870. if (pt->synth_opts.ptwrites) {
  1871. attr.config = PERF_SYNTH_INTEL_PTWRITE;
  1872. err = intel_pt_synth_event(session, "ptwrite", &attr, id);
  1873. if (err)
  1874. return err;
  1875. pt->sample_ptwrites = true;
  1876. pt->ptwrites_sample_type = attr.sample_type;
  1877. pt->ptwrites_id = id;
  1878. intel_pt_set_event_name(evlist, id, "ptwrite");
  1879. id += 1;
  1880. }
  1881. if (pt->synth_opts.pwr_events) {
  1882. pt->sample_pwr_events = true;
  1883. pt->pwr_events_sample_type = attr.sample_type;
  1884. attr.config = PERF_SYNTH_INTEL_CBR;
  1885. err = intel_pt_synth_event(session, "cbr", &attr, id);
  1886. if (err)
  1887. return err;
  1888. pt->cbr_id = id;
  1889. intel_pt_set_event_name(evlist, id, "cbr");
  1890. id += 1;
  1891. }
  1892. if (pt->synth_opts.pwr_events && (evsel->attr.config & 0x10)) {
  1893. attr.config = PERF_SYNTH_INTEL_MWAIT;
  1894. err = intel_pt_synth_event(session, "mwait", &attr, id);
  1895. if (err)
  1896. return err;
  1897. pt->mwait_id = id;
  1898. intel_pt_set_event_name(evlist, id, "mwait");
  1899. id += 1;
  1900. attr.config = PERF_SYNTH_INTEL_PWRE;
  1901. err = intel_pt_synth_event(session, "pwre", &attr, id);
  1902. if (err)
  1903. return err;
  1904. pt->pwre_id = id;
  1905. intel_pt_set_event_name(evlist, id, "pwre");
  1906. id += 1;
  1907. attr.config = PERF_SYNTH_INTEL_EXSTOP;
  1908. err = intel_pt_synth_event(session, "exstop", &attr, id);
  1909. if (err)
  1910. return err;
  1911. pt->exstop_id = id;
  1912. intel_pt_set_event_name(evlist, id, "exstop");
  1913. id += 1;
  1914. attr.config = PERF_SYNTH_INTEL_PWRX;
  1915. err = intel_pt_synth_event(session, "pwrx", &attr, id);
  1916. if (err)
  1917. return err;
  1918. pt->pwrx_id = id;
  1919. intel_pt_set_event_name(evlist, id, "pwrx");
  1920. id += 1;
  1921. }
  1922. return 0;
  1923. }
  1924. static struct perf_evsel *intel_pt_find_sched_switch(struct perf_evlist *evlist)
  1925. {
  1926. struct perf_evsel *evsel;
  1927. evlist__for_each_entry_reverse(evlist, evsel) {
  1928. const char *name = perf_evsel__name(evsel);
  1929. if (!strcmp(name, "sched:sched_switch"))
  1930. return evsel;
  1931. }
  1932. return NULL;
  1933. }
  1934. static bool intel_pt_find_switch(struct perf_evlist *evlist)
  1935. {
  1936. struct perf_evsel *evsel;
  1937. evlist__for_each_entry(evlist, evsel) {
  1938. if (evsel->attr.context_switch)
  1939. return true;
  1940. }
  1941. return false;
  1942. }
  1943. static int intel_pt_perf_config(const char *var, const char *value, void *data)
  1944. {
  1945. struct intel_pt *pt = data;
  1946. if (!strcmp(var, "intel-pt.mispred-all"))
  1947. pt->mispred_all = perf_config_bool(var, value);
  1948. return 0;
  1949. }
  1950. static const char * const intel_pt_info_fmts[] = {
  1951. [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
  1952. [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
  1953. [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
  1954. [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
  1955. [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
  1956. [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
  1957. [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
  1958. [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
  1959. [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
  1960. [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
  1961. [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
  1962. [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
  1963. [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
  1964. [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
  1965. [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
  1966. [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
  1967. };
  1968. static void intel_pt_print_info(u64 *arr, int start, int finish)
  1969. {
  1970. int i;
  1971. if (!dump_trace)
  1972. return;
  1973. for (i = start; i <= finish; i++)
  1974. fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
  1975. }
  1976. static void intel_pt_print_info_str(const char *name, const char *str)
  1977. {
  1978. if (!dump_trace)
  1979. return;
  1980. fprintf(stdout, " %-20s%s\n", name, str ? str : "");
  1981. }
  1982. static bool intel_pt_has(struct auxtrace_info_event *auxtrace_info, int pos)
  1983. {
  1984. return auxtrace_info->header.size >=
  1985. sizeof(struct auxtrace_info_event) + (sizeof(u64) * (pos + 1));
  1986. }
  1987. int intel_pt_process_auxtrace_info(union perf_event *event,
  1988. struct perf_session *session)
  1989. {
  1990. struct auxtrace_info_event *auxtrace_info = &event->auxtrace_info;
  1991. size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
  1992. struct intel_pt *pt;
  1993. void *info_end;
  1994. u64 *info;
  1995. int err;
  1996. if (auxtrace_info->header.size < sizeof(struct auxtrace_info_event) +
  1997. min_sz)
  1998. return -EINVAL;
  1999. pt = zalloc(sizeof(struct intel_pt));
  2000. if (!pt)
  2001. return -ENOMEM;
  2002. addr_filters__init(&pt->filts);
  2003. err = perf_config(intel_pt_perf_config, pt);
  2004. if (err)
  2005. goto err_free;
  2006. err = auxtrace_queues__init(&pt->queues);
  2007. if (err)
  2008. goto err_free;
  2009. intel_pt_log_set_name(INTEL_PT_PMU_NAME);
  2010. pt->session = session;
  2011. pt->machine = &session->machines.host; /* No kvm support */
  2012. pt->auxtrace_type = auxtrace_info->type;
  2013. pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
  2014. pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
  2015. pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
  2016. pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
  2017. pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
  2018. pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
  2019. pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
  2020. pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
  2021. pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
  2022. pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
  2023. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
  2024. INTEL_PT_PER_CPU_MMAPS);
  2025. if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
  2026. pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
  2027. pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
  2028. pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
  2029. pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
  2030. pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
  2031. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
  2032. INTEL_PT_CYC_BIT);
  2033. }
  2034. if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
  2035. pt->max_non_turbo_ratio =
  2036. auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
  2037. intel_pt_print_info(&auxtrace_info->priv[0],
  2038. INTEL_PT_MAX_NONTURBO_RATIO,
  2039. INTEL_PT_MAX_NONTURBO_RATIO);
  2040. }
  2041. info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
  2042. info_end = (void *)info + auxtrace_info->header.size;
  2043. if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
  2044. size_t len;
  2045. len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
  2046. intel_pt_print_info(&auxtrace_info->priv[0],
  2047. INTEL_PT_FILTER_STR_LEN,
  2048. INTEL_PT_FILTER_STR_LEN);
  2049. if (len) {
  2050. const char *filter = (const char *)info;
  2051. len = roundup(len + 1, 8);
  2052. info += len >> 3;
  2053. if ((void *)info > info_end) {
  2054. pr_err("%s: bad filter string length\n", __func__);
  2055. err = -EINVAL;
  2056. goto err_free_queues;
  2057. }
  2058. pt->filter = memdup(filter, len);
  2059. if (!pt->filter) {
  2060. err = -ENOMEM;
  2061. goto err_free_queues;
  2062. }
  2063. if (session->header.needs_swap)
  2064. mem_bswap_64(pt->filter, len);
  2065. if (pt->filter[len - 1]) {
  2066. pr_err("%s: filter string not null terminated\n", __func__);
  2067. err = -EINVAL;
  2068. goto err_free_queues;
  2069. }
  2070. err = addr_filters__parse_bare_filter(&pt->filts,
  2071. filter);
  2072. if (err)
  2073. goto err_free_queues;
  2074. }
  2075. intel_pt_print_info_str("Filter string", pt->filter);
  2076. }
  2077. pt->timeless_decoding = intel_pt_timeless_decoding(pt);
  2078. pt->have_tsc = intel_pt_have_tsc(pt);
  2079. pt->sampling_mode = false;
  2080. pt->est_tsc = !pt->timeless_decoding;
  2081. pt->unknown_thread = thread__new(999999999, 999999999);
  2082. if (!pt->unknown_thread) {
  2083. err = -ENOMEM;
  2084. goto err_free_queues;
  2085. }
  2086. /*
  2087. * Since this thread will not be kept in any rbtree not in a
  2088. * list, initialize its list node so that at thread__put() the
  2089. * current thread lifetime assuption is kept and we don't segfault
  2090. * at list_del_init().
  2091. */
  2092. INIT_LIST_HEAD(&pt->unknown_thread->node);
  2093. err = thread__set_comm(pt->unknown_thread, "unknown", 0);
  2094. if (err)
  2095. goto err_delete_thread;
  2096. if (thread__init_map_groups(pt->unknown_thread, pt->machine)) {
  2097. err = -ENOMEM;
  2098. goto err_delete_thread;
  2099. }
  2100. pt->auxtrace.process_event = intel_pt_process_event;
  2101. pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
  2102. pt->auxtrace.flush_events = intel_pt_flush;
  2103. pt->auxtrace.free_events = intel_pt_free_events;
  2104. pt->auxtrace.free = intel_pt_free;
  2105. session->auxtrace = &pt->auxtrace;
  2106. if (dump_trace)
  2107. return 0;
  2108. if (pt->have_sched_switch == 1) {
  2109. pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
  2110. if (!pt->switch_evsel) {
  2111. pr_err("%s: missing sched_switch event\n", __func__);
  2112. err = -EINVAL;
  2113. goto err_delete_thread;
  2114. }
  2115. } else if (pt->have_sched_switch == 2 &&
  2116. !intel_pt_find_switch(session->evlist)) {
  2117. pr_err("%s: missing context_switch attribute flag\n", __func__);
  2118. err = -EINVAL;
  2119. goto err_delete_thread;
  2120. }
  2121. if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
  2122. pt->synth_opts = *session->itrace_synth_opts;
  2123. } else {
  2124. itrace_synth_opts__set_default(&pt->synth_opts,
  2125. session->itrace_synth_opts->default_no_sample);
  2126. if (use_browser != -1) {
  2127. pt->synth_opts.branches = false;
  2128. pt->synth_opts.callchain = true;
  2129. }
  2130. if (session->itrace_synth_opts)
  2131. pt->synth_opts.thread_stack =
  2132. session->itrace_synth_opts->thread_stack;
  2133. }
  2134. if (pt->synth_opts.log)
  2135. intel_pt_log_enable();
  2136. /* Maximum non-turbo ratio is TSC freq / 100 MHz */
  2137. if (pt->tc.time_mult) {
  2138. u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
  2139. if (!pt->max_non_turbo_ratio)
  2140. pt->max_non_turbo_ratio =
  2141. (tsc_freq + 50000000) / 100000000;
  2142. intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
  2143. intel_pt_log("Maximum non-turbo ratio %u\n",
  2144. pt->max_non_turbo_ratio);
  2145. pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
  2146. }
  2147. if (pt->synth_opts.calls)
  2148. pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
  2149. PERF_IP_FLAG_TRACE_END;
  2150. if (pt->synth_opts.returns)
  2151. pt->branches_filter |= PERF_IP_FLAG_RETURN |
  2152. PERF_IP_FLAG_TRACE_BEGIN;
  2153. if (pt->synth_opts.callchain && !symbol_conf.use_callchain) {
  2154. symbol_conf.use_callchain = true;
  2155. if (callchain_register_param(&callchain_param) < 0) {
  2156. symbol_conf.use_callchain = false;
  2157. pt->synth_opts.callchain = false;
  2158. }
  2159. }
  2160. err = intel_pt_synth_events(pt, session);
  2161. if (err)
  2162. goto err_delete_thread;
  2163. err = auxtrace_queues__process_index(&pt->queues, session);
  2164. if (err)
  2165. goto err_delete_thread;
  2166. if (pt->queues.populated)
  2167. pt->data_queued = true;
  2168. if (pt->timeless_decoding)
  2169. pr_debug2("Intel PT decoding without timestamps\n");
  2170. return 0;
  2171. err_delete_thread:
  2172. thread__zput(pt->unknown_thread);
  2173. err_free_queues:
  2174. intel_pt_log_disable();
  2175. auxtrace_queues__free(&pt->queues);
  2176. session->auxtrace = NULL;
  2177. err_free:
  2178. addr_filters__exit(&pt->filts);
  2179. zfree(&pt->filter);
  2180. free(pt);
  2181. return err;
  2182. }