dbdma2.c 9.3 KB

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  1. /*
  2. * Au12x0/Au1550 PSC ALSA ASoC audio support.
  3. *
  4. * (c) 2007-2008 MSC Vertriebsges.m.b.H.,
  5. * Manuel Lauss <manuel.lauss@gmail.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * DMA glue for Au1x-PSC audio.
  12. *
  13. */
  14. #include <linux/module.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/dma-mapping.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <asm/mach-au1x00/au1000.h>
  24. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  25. #include <asm/mach-au1x00/au1xxx_psc.h>
  26. #include "psc.h"
  27. /*#define PCM_DEBUG*/
  28. #define DRV_NAME "dbdma2"
  29. #define MSG(x...) printk(KERN_INFO "au1xpsc_pcm: " x)
  30. #ifdef PCM_DEBUG
  31. #define DBG MSG
  32. #else
  33. #define DBG(x...) do {} while (0)
  34. #endif
  35. struct au1xpsc_audio_dmadata {
  36. /* DDMA control data */
  37. unsigned int ddma_id; /* DDMA direction ID for this PSC */
  38. u32 ddma_chan; /* DDMA context */
  39. /* PCM context (for irq handlers) */
  40. struct snd_pcm_substream *substream;
  41. unsigned long curr_period; /* current segment DDMA is working on */
  42. unsigned long q_period; /* queue period(s) */
  43. dma_addr_t dma_area; /* address of queued DMA area */
  44. dma_addr_t dma_area_s; /* start address of DMA area */
  45. unsigned long pos; /* current byte position being played */
  46. unsigned long periods; /* number of SG segments in total */
  47. unsigned long period_bytes; /* size in bytes of one SG segment */
  48. /* runtime data */
  49. int msbits;
  50. };
  51. /*
  52. * These settings are somewhat okay, at least on my machine audio plays
  53. * almost skip-free. Especially the 64kB buffer seems to help a LOT.
  54. */
  55. #define AU1XPSC_PERIOD_MIN_BYTES 1024
  56. #define AU1XPSC_BUFFER_MIN_BYTES 65536
  57. /* PCM hardware DMA capabilities - platform specific */
  58. static const struct snd_pcm_hardware au1xpsc_pcm_hardware = {
  59. .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
  60. SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BATCH,
  61. .period_bytes_min = AU1XPSC_PERIOD_MIN_BYTES,
  62. .period_bytes_max = 4096 * 1024 - 1,
  63. .periods_min = 2,
  64. .periods_max = 4096, /* 2 to as-much-as-you-like */
  65. .buffer_bytes_max = 4096 * 1024 - 1,
  66. .fifo_size = 16, /* fifo entries of AC97/I2S PSC */
  67. };
  68. static void au1x_pcm_queue_tx(struct au1xpsc_audio_dmadata *cd)
  69. {
  70. au1xxx_dbdma_put_source(cd->ddma_chan, cd->dma_area,
  71. cd->period_bytes, DDMA_FLAGS_IE);
  72. /* update next-to-queue period */
  73. ++cd->q_period;
  74. cd->dma_area += cd->period_bytes;
  75. if (cd->q_period >= cd->periods) {
  76. cd->q_period = 0;
  77. cd->dma_area = cd->dma_area_s;
  78. }
  79. }
  80. static void au1x_pcm_queue_rx(struct au1xpsc_audio_dmadata *cd)
  81. {
  82. au1xxx_dbdma_put_dest(cd->ddma_chan, cd->dma_area,
  83. cd->period_bytes, DDMA_FLAGS_IE);
  84. /* update next-to-queue period */
  85. ++cd->q_period;
  86. cd->dma_area += cd->period_bytes;
  87. if (cd->q_period >= cd->periods) {
  88. cd->q_period = 0;
  89. cd->dma_area = cd->dma_area_s;
  90. }
  91. }
  92. static void au1x_pcm_dmatx_cb(int irq, void *dev_id)
  93. {
  94. struct au1xpsc_audio_dmadata *cd = dev_id;
  95. cd->pos += cd->period_bytes;
  96. if (++cd->curr_period >= cd->periods) {
  97. cd->pos = 0;
  98. cd->curr_period = 0;
  99. }
  100. snd_pcm_period_elapsed(cd->substream);
  101. au1x_pcm_queue_tx(cd);
  102. }
  103. static void au1x_pcm_dmarx_cb(int irq, void *dev_id)
  104. {
  105. struct au1xpsc_audio_dmadata *cd = dev_id;
  106. cd->pos += cd->period_bytes;
  107. if (++cd->curr_period >= cd->periods) {
  108. cd->pos = 0;
  109. cd->curr_period = 0;
  110. }
  111. snd_pcm_period_elapsed(cd->substream);
  112. au1x_pcm_queue_rx(cd);
  113. }
  114. static void au1x_pcm_dbdma_free(struct au1xpsc_audio_dmadata *pcd)
  115. {
  116. if (pcd->ddma_chan) {
  117. au1xxx_dbdma_stop(pcd->ddma_chan);
  118. au1xxx_dbdma_reset(pcd->ddma_chan);
  119. au1xxx_dbdma_chan_free(pcd->ddma_chan);
  120. pcd->ddma_chan = 0;
  121. pcd->msbits = 0;
  122. }
  123. }
  124. /* in case of missing DMA ring or changed TX-source / RX-dest bit widths,
  125. * allocate (or reallocate) a 2-descriptor DMA ring with bit depth according
  126. * to ALSA-supplied sample depth. This is due to limitations in the dbdma api
  127. * (cannot adjust source/dest widths of already allocated descriptor ring).
  128. */
  129. static int au1x_pcm_dbdma_realloc(struct au1xpsc_audio_dmadata *pcd,
  130. int stype, int msbits)
  131. {
  132. /* DMA only in 8/16/32 bit widths */
  133. if (msbits == 24)
  134. msbits = 32;
  135. /* check current config: correct bits and descriptors allocated? */
  136. if ((pcd->ddma_chan) && (msbits == pcd->msbits))
  137. goto out; /* all ok! */
  138. au1x_pcm_dbdma_free(pcd);
  139. if (stype == SNDRV_PCM_STREAM_CAPTURE)
  140. pcd->ddma_chan = au1xxx_dbdma_chan_alloc(pcd->ddma_id,
  141. DSCR_CMD0_ALWAYS,
  142. au1x_pcm_dmarx_cb, (void *)pcd);
  143. else
  144. pcd->ddma_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
  145. pcd->ddma_id,
  146. au1x_pcm_dmatx_cb, (void *)pcd);
  147. if (!pcd->ddma_chan)
  148. return -ENOMEM;
  149. au1xxx_dbdma_set_devwidth(pcd->ddma_chan, msbits);
  150. au1xxx_dbdma_ring_alloc(pcd->ddma_chan, 2);
  151. pcd->msbits = msbits;
  152. au1xxx_dbdma_stop(pcd->ddma_chan);
  153. au1xxx_dbdma_reset(pcd->ddma_chan);
  154. out:
  155. return 0;
  156. }
  157. static inline struct au1xpsc_audio_dmadata *to_dmadata(struct snd_pcm_substream *ss)
  158. {
  159. struct snd_soc_pcm_runtime *rtd = ss->private_data;
  160. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
  161. struct au1xpsc_audio_dmadata *pcd = snd_soc_component_get_drvdata(component);
  162. return &pcd[ss->stream];
  163. }
  164. static int au1xpsc_pcm_hw_params(struct snd_pcm_substream *substream,
  165. struct snd_pcm_hw_params *params)
  166. {
  167. struct snd_pcm_runtime *runtime = substream->runtime;
  168. struct au1xpsc_audio_dmadata *pcd;
  169. int stype, ret;
  170. ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
  171. if (ret < 0)
  172. goto out;
  173. stype = substream->stream;
  174. pcd = to_dmadata(substream);
  175. DBG("runtime->dma_area = 0x%08lx dma_addr_t = 0x%08lx dma_size = %zu "
  176. "runtime->min_align %lu\n",
  177. (unsigned long)runtime->dma_area,
  178. (unsigned long)runtime->dma_addr, runtime->dma_bytes,
  179. runtime->min_align);
  180. DBG("bits %d frags %d frag_bytes %d is_rx %d\n", params->msbits,
  181. params_periods(params), params_period_bytes(params), stype);
  182. ret = au1x_pcm_dbdma_realloc(pcd, stype, params->msbits);
  183. if (ret) {
  184. MSG("DDMA channel (re)alloc failed!\n");
  185. goto out;
  186. }
  187. pcd->substream = substream;
  188. pcd->period_bytes = params_period_bytes(params);
  189. pcd->periods = params_periods(params);
  190. pcd->dma_area_s = pcd->dma_area = runtime->dma_addr;
  191. pcd->q_period = 0;
  192. pcd->curr_period = 0;
  193. pcd->pos = 0;
  194. ret = 0;
  195. out:
  196. return ret;
  197. }
  198. static int au1xpsc_pcm_hw_free(struct snd_pcm_substream *substream)
  199. {
  200. snd_pcm_lib_free_pages(substream);
  201. return 0;
  202. }
  203. static int au1xpsc_pcm_prepare(struct snd_pcm_substream *substream)
  204. {
  205. struct au1xpsc_audio_dmadata *pcd = to_dmadata(substream);
  206. au1xxx_dbdma_reset(pcd->ddma_chan);
  207. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  208. au1x_pcm_queue_rx(pcd);
  209. au1x_pcm_queue_rx(pcd);
  210. } else {
  211. au1x_pcm_queue_tx(pcd);
  212. au1x_pcm_queue_tx(pcd);
  213. }
  214. return 0;
  215. }
  216. static int au1xpsc_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  217. {
  218. u32 c = to_dmadata(substream)->ddma_chan;
  219. switch (cmd) {
  220. case SNDRV_PCM_TRIGGER_START:
  221. case SNDRV_PCM_TRIGGER_RESUME:
  222. au1xxx_dbdma_start(c);
  223. break;
  224. case SNDRV_PCM_TRIGGER_STOP:
  225. case SNDRV_PCM_TRIGGER_SUSPEND:
  226. au1xxx_dbdma_stop(c);
  227. break;
  228. default:
  229. return -EINVAL;
  230. }
  231. return 0;
  232. }
  233. static snd_pcm_uframes_t
  234. au1xpsc_pcm_pointer(struct snd_pcm_substream *substream)
  235. {
  236. return bytes_to_frames(substream->runtime, to_dmadata(substream)->pos);
  237. }
  238. static int au1xpsc_pcm_open(struct snd_pcm_substream *substream)
  239. {
  240. struct au1xpsc_audio_dmadata *pcd = to_dmadata(substream);
  241. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  242. int stype = substream->stream, *dmaids;
  243. dmaids = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  244. if (!dmaids)
  245. return -ENODEV; /* whoa, has ordering changed? */
  246. pcd->ddma_id = dmaids[stype];
  247. snd_soc_set_runtime_hwparams(substream, &au1xpsc_pcm_hardware);
  248. return 0;
  249. }
  250. static int au1xpsc_pcm_close(struct snd_pcm_substream *substream)
  251. {
  252. au1x_pcm_dbdma_free(to_dmadata(substream));
  253. return 0;
  254. }
  255. static const struct snd_pcm_ops au1xpsc_pcm_ops = {
  256. .open = au1xpsc_pcm_open,
  257. .close = au1xpsc_pcm_close,
  258. .ioctl = snd_pcm_lib_ioctl,
  259. .hw_params = au1xpsc_pcm_hw_params,
  260. .hw_free = au1xpsc_pcm_hw_free,
  261. .prepare = au1xpsc_pcm_prepare,
  262. .trigger = au1xpsc_pcm_trigger,
  263. .pointer = au1xpsc_pcm_pointer,
  264. };
  265. static int au1xpsc_pcm_new(struct snd_soc_pcm_runtime *rtd)
  266. {
  267. struct snd_card *card = rtd->card->snd_card;
  268. struct snd_pcm *pcm = rtd->pcm;
  269. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  270. card->dev, AU1XPSC_BUFFER_MIN_BYTES, (4096 * 1024) - 1);
  271. return 0;
  272. }
  273. /* au1xpsc audio platform */
  274. static struct snd_soc_component_driver au1xpsc_soc_component = {
  275. .name = DRV_NAME,
  276. .ops = &au1xpsc_pcm_ops,
  277. .pcm_new = au1xpsc_pcm_new,
  278. };
  279. static int au1xpsc_pcm_drvprobe(struct platform_device *pdev)
  280. {
  281. struct au1xpsc_audio_dmadata *dmadata;
  282. dmadata = devm_kcalloc(&pdev->dev,
  283. 2, sizeof(struct au1xpsc_audio_dmadata),
  284. GFP_KERNEL);
  285. if (!dmadata)
  286. return -ENOMEM;
  287. platform_set_drvdata(pdev, dmadata);
  288. return devm_snd_soc_register_component(&pdev->dev,
  289. &au1xpsc_soc_component, NULL, 0);
  290. }
  291. static struct platform_driver au1xpsc_pcm_driver = {
  292. .driver = {
  293. .name = "au1xpsc-pcm",
  294. },
  295. .probe = au1xpsc_pcm_drvprobe,
  296. };
  297. module_platform_driver(au1xpsc_pcm_driver);
  298. MODULE_LICENSE("GPL");
  299. MODULE_DESCRIPTION("Au12x0/Au1550 PSC Audio DMA driver");
  300. MODULE_AUTHOR("Manuel Lauss");