xhci-dbgcap.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * xhci-dbgcap.c - xHCI debug capability support
  4. *
  5. * Copyright (C) 2017 Intel Corporation
  6. *
  7. * Author: Lu Baolu <baolu.lu@linux.intel.com>
  8. */
  9. #include <linux/dma-mapping.h>
  10. #include <linux/slab.h>
  11. #include <linux/nls.h>
  12. #include "xhci.h"
  13. #include "xhci-trace.h"
  14. #include "xhci-dbgcap.h"
  15. static inline void *
  16. dbc_dma_alloc_coherent(struct xhci_hcd *xhci, size_t size,
  17. dma_addr_t *dma_handle, gfp_t flags)
  18. {
  19. void *vaddr;
  20. vaddr = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
  21. size, dma_handle, flags);
  22. memset(vaddr, 0, size);
  23. return vaddr;
  24. }
  25. static inline void
  26. dbc_dma_free_coherent(struct xhci_hcd *xhci, size_t size,
  27. void *cpu_addr, dma_addr_t dma_handle)
  28. {
  29. if (cpu_addr)
  30. dma_free_coherent(xhci_to_hcd(xhci)->self.sysdev,
  31. size, cpu_addr, dma_handle);
  32. }
  33. static u32 xhci_dbc_populate_strings(struct dbc_str_descs *strings)
  34. {
  35. struct usb_string_descriptor *s_desc;
  36. u32 string_length;
  37. /* Serial string: */
  38. s_desc = (struct usb_string_descriptor *)strings->serial;
  39. utf8s_to_utf16s(DBC_STRING_SERIAL, strlen(DBC_STRING_SERIAL),
  40. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  41. DBC_MAX_STRING_LENGTH);
  42. s_desc->bLength = (strlen(DBC_STRING_SERIAL) + 1) * 2;
  43. s_desc->bDescriptorType = USB_DT_STRING;
  44. string_length = s_desc->bLength;
  45. string_length <<= 8;
  46. /* Product string: */
  47. s_desc = (struct usb_string_descriptor *)strings->product;
  48. utf8s_to_utf16s(DBC_STRING_PRODUCT, strlen(DBC_STRING_PRODUCT),
  49. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  50. DBC_MAX_STRING_LENGTH);
  51. s_desc->bLength = (strlen(DBC_STRING_PRODUCT) + 1) * 2;
  52. s_desc->bDescriptorType = USB_DT_STRING;
  53. string_length += s_desc->bLength;
  54. string_length <<= 8;
  55. /* Manufacture string: */
  56. s_desc = (struct usb_string_descriptor *)strings->manufacturer;
  57. utf8s_to_utf16s(DBC_STRING_MANUFACTURER,
  58. strlen(DBC_STRING_MANUFACTURER),
  59. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  60. DBC_MAX_STRING_LENGTH);
  61. s_desc->bLength = (strlen(DBC_STRING_MANUFACTURER) + 1) * 2;
  62. s_desc->bDescriptorType = USB_DT_STRING;
  63. string_length += s_desc->bLength;
  64. string_length <<= 8;
  65. /* String0: */
  66. strings->string0[0] = 4;
  67. strings->string0[1] = USB_DT_STRING;
  68. strings->string0[2] = 0x09;
  69. strings->string0[3] = 0x04;
  70. string_length += 4;
  71. return string_length;
  72. }
  73. static void xhci_dbc_init_contexts(struct xhci_hcd *xhci, u32 string_length)
  74. {
  75. struct xhci_dbc *dbc;
  76. struct dbc_info_context *info;
  77. struct xhci_ep_ctx *ep_ctx;
  78. u32 dev_info;
  79. dma_addr_t deq, dma;
  80. unsigned int max_burst;
  81. dbc = xhci->dbc;
  82. if (!dbc)
  83. return;
  84. /* Populate info Context: */
  85. info = (struct dbc_info_context *)dbc->ctx->bytes;
  86. dma = dbc->string_dma;
  87. info->string0 = cpu_to_le64(dma);
  88. info->manufacturer = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH);
  89. info->product = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 2);
  90. info->serial = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 3);
  91. info->length = cpu_to_le32(string_length);
  92. /* Populate bulk out endpoint context: */
  93. ep_ctx = dbc_bulkout_ctx(dbc);
  94. max_burst = DBC_CTRL_MAXBURST(readl(&dbc->regs->control));
  95. deq = dbc_bulkout_enq(dbc);
  96. ep_ctx->ep_info = 0;
  97. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_OUT_EP, 1024, max_burst);
  98. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_out->cycle_state);
  99. /* Populate bulk in endpoint context: */
  100. ep_ctx = dbc_bulkin_ctx(dbc);
  101. deq = dbc_bulkin_enq(dbc);
  102. ep_ctx->ep_info = 0;
  103. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_IN_EP, 1024, max_burst);
  104. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_in->cycle_state);
  105. /* Set DbC context and info registers: */
  106. xhci_write_64(xhci, dbc->ctx->dma, &dbc->regs->dccp);
  107. dev_info = cpu_to_le32((DBC_VENDOR_ID << 16) | DBC_PROTOCOL);
  108. writel(dev_info, &dbc->regs->devinfo1);
  109. dev_info = cpu_to_le32((DBC_DEVICE_REV << 16) | DBC_PRODUCT_ID);
  110. writel(dev_info, &dbc->regs->devinfo2);
  111. }
  112. static void xhci_dbc_giveback(struct dbc_request *req, int status)
  113. __releases(&dbc->lock)
  114. __acquires(&dbc->lock)
  115. {
  116. struct dbc_ep *dep = req->dep;
  117. struct xhci_dbc *dbc = dep->dbc;
  118. struct xhci_hcd *xhci = dbc->xhci;
  119. struct device *dev = xhci_to_hcd(dbc->xhci)->self.sysdev;
  120. list_del_init(&req->list_pending);
  121. req->trb_dma = 0;
  122. req->trb = NULL;
  123. if (req->status == -EINPROGRESS)
  124. req->status = status;
  125. trace_xhci_dbc_giveback_request(req);
  126. dma_unmap_single(dev,
  127. req->dma,
  128. req->length,
  129. dbc_ep_dma_direction(dep));
  130. /* Give back the transfer request: */
  131. spin_unlock(&dbc->lock);
  132. req->complete(xhci, req);
  133. spin_lock(&dbc->lock);
  134. }
  135. static void xhci_dbc_flush_single_request(struct dbc_request *req)
  136. {
  137. union xhci_trb *trb = req->trb;
  138. trb->generic.field[0] = 0;
  139. trb->generic.field[1] = 0;
  140. trb->generic.field[2] = 0;
  141. trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
  142. trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(TRB_TR_NOOP));
  143. xhci_dbc_giveback(req, -ESHUTDOWN);
  144. }
  145. static void xhci_dbc_flush_endpoint_requests(struct dbc_ep *dep)
  146. {
  147. struct dbc_request *req, *tmp;
  148. list_for_each_entry_safe(req, tmp, &dep->list_pending, list_pending)
  149. xhci_dbc_flush_single_request(req);
  150. }
  151. static void xhci_dbc_flush_reqests(struct xhci_dbc *dbc)
  152. {
  153. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_OUT]);
  154. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_IN]);
  155. }
  156. struct dbc_request *
  157. dbc_alloc_request(struct dbc_ep *dep, gfp_t gfp_flags)
  158. {
  159. struct dbc_request *req;
  160. req = kzalloc(sizeof(*req), gfp_flags);
  161. if (!req)
  162. return NULL;
  163. req->dep = dep;
  164. INIT_LIST_HEAD(&req->list_pending);
  165. INIT_LIST_HEAD(&req->list_pool);
  166. req->direction = dep->direction;
  167. trace_xhci_dbc_alloc_request(req);
  168. return req;
  169. }
  170. void
  171. dbc_free_request(struct dbc_ep *dep, struct dbc_request *req)
  172. {
  173. trace_xhci_dbc_free_request(req);
  174. kfree(req);
  175. }
  176. static void
  177. xhci_dbc_queue_trb(struct xhci_ring *ring, u32 field1,
  178. u32 field2, u32 field3, u32 field4)
  179. {
  180. union xhci_trb *trb, *next;
  181. trb = ring->enqueue;
  182. trb->generic.field[0] = cpu_to_le32(field1);
  183. trb->generic.field[1] = cpu_to_le32(field2);
  184. trb->generic.field[2] = cpu_to_le32(field3);
  185. trb->generic.field[3] = cpu_to_le32(field4);
  186. trace_xhci_dbc_gadget_ep_queue(ring, &trb->generic);
  187. ring->num_trbs_free--;
  188. next = ++(ring->enqueue);
  189. if (TRB_TYPE_LINK_LE32(next->link.control)) {
  190. next->link.control ^= cpu_to_le32(TRB_CYCLE);
  191. ring->enqueue = ring->enq_seg->trbs;
  192. ring->cycle_state ^= 1;
  193. }
  194. }
  195. static int xhci_dbc_queue_bulk_tx(struct dbc_ep *dep,
  196. struct dbc_request *req)
  197. {
  198. u64 addr;
  199. union xhci_trb *trb;
  200. unsigned int num_trbs;
  201. struct xhci_dbc *dbc = dep->dbc;
  202. struct xhci_ring *ring = dep->ring;
  203. u32 length, control, cycle;
  204. num_trbs = count_trbs(req->dma, req->length);
  205. WARN_ON(num_trbs != 1);
  206. if (ring->num_trbs_free < num_trbs)
  207. return -EBUSY;
  208. addr = req->dma;
  209. trb = ring->enqueue;
  210. cycle = ring->cycle_state;
  211. length = TRB_LEN(req->length);
  212. control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
  213. if (cycle)
  214. control &= cpu_to_le32(~TRB_CYCLE);
  215. else
  216. control |= cpu_to_le32(TRB_CYCLE);
  217. req->trb = ring->enqueue;
  218. req->trb_dma = xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
  219. xhci_dbc_queue_trb(ring,
  220. lower_32_bits(addr),
  221. upper_32_bits(addr),
  222. length, control);
  223. /*
  224. * Add a barrier between writes of trb fields and flipping
  225. * the cycle bit:
  226. */
  227. wmb();
  228. if (cycle)
  229. trb->generic.field[3] |= cpu_to_le32(TRB_CYCLE);
  230. else
  231. trb->generic.field[3] &= cpu_to_le32(~TRB_CYCLE);
  232. writel(DBC_DOOR_BELL_TARGET(dep->direction), &dbc->regs->doorbell);
  233. return 0;
  234. }
  235. static int
  236. dbc_ep_do_queue(struct dbc_ep *dep, struct dbc_request *req)
  237. {
  238. int ret;
  239. struct device *dev;
  240. struct xhci_dbc *dbc = dep->dbc;
  241. struct xhci_hcd *xhci = dbc->xhci;
  242. dev = xhci_to_hcd(xhci)->self.sysdev;
  243. if (!req->length || !req->buf)
  244. return -EINVAL;
  245. req->actual = 0;
  246. req->status = -EINPROGRESS;
  247. req->dma = dma_map_single(dev,
  248. req->buf,
  249. req->length,
  250. dbc_ep_dma_direction(dep));
  251. if (dma_mapping_error(dev, req->dma)) {
  252. xhci_err(xhci, "failed to map buffer\n");
  253. return -EFAULT;
  254. }
  255. ret = xhci_dbc_queue_bulk_tx(dep, req);
  256. if (ret) {
  257. xhci_err(xhci, "failed to queue trbs\n");
  258. dma_unmap_single(dev,
  259. req->dma,
  260. req->length,
  261. dbc_ep_dma_direction(dep));
  262. return -EFAULT;
  263. }
  264. list_add_tail(&req->list_pending, &dep->list_pending);
  265. return 0;
  266. }
  267. int dbc_ep_queue(struct dbc_ep *dep, struct dbc_request *req,
  268. gfp_t gfp_flags)
  269. {
  270. unsigned long flags;
  271. struct xhci_dbc *dbc = dep->dbc;
  272. int ret = -ESHUTDOWN;
  273. spin_lock_irqsave(&dbc->lock, flags);
  274. if (dbc->state == DS_CONFIGURED)
  275. ret = dbc_ep_do_queue(dep, req);
  276. spin_unlock_irqrestore(&dbc->lock, flags);
  277. mod_delayed_work(system_wq, &dbc->event_work, 0);
  278. trace_xhci_dbc_queue_request(req);
  279. return ret;
  280. }
  281. static inline void xhci_dbc_do_eps_init(struct xhci_hcd *xhci, bool direction)
  282. {
  283. struct dbc_ep *dep;
  284. struct xhci_dbc *dbc = xhci->dbc;
  285. dep = &dbc->eps[direction];
  286. dep->dbc = dbc;
  287. dep->direction = direction;
  288. dep->ring = direction ? dbc->ring_in : dbc->ring_out;
  289. INIT_LIST_HEAD(&dep->list_pending);
  290. }
  291. static void xhci_dbc_eps_init(struct xhci_hcd *xhci)
  292. {
  293. xhci_dbc_do_eps_init(xhci, BULK_OUT);
  294. xhci_dbc_do_eps_init(xhci, BULK_IN);
  295. }
  296. static void xhci_dbc_eps_exit(struct xhci_hcd *xhci)
  297. {
  298. struct xhci_dbc *dbc = xhci->dbc;
  299. memset(dbc->eps, 0, sizeof(struct dbc_ep) * ARRAY_SIZE(dbc->eps));
  300. }
  301. static int xhci_dbc_mem_init(struct xhci_hcd *xhci, gfp_t flags)
  302. {
  303. int ret;
  304. dma_addr_t deq;
  305. u32 string_length;
  306. struct xhci_dbc *dbc = xhci->dbc;
  307. /* Allocate various rings for events and transfers: */
  308. dbc->ring_evt = xhci_ring_alloc(xhci, 1, 1, TYPE_EVENT, 0, flags);
  309. if (!dbc->ring_evt)
  310. goto evt_fail;
  311. dbc->ring_in = xhci_ring_alloc(xhci, 1, 1, TYPE_BULK, 0, flags);
  312. if (!dbc->ring_in)
  313. goto in_fail;
  314. dbc->ring_out = xhci_ring_alloc(xhci, 1, 1, TYPE_BULK, 0, flags);
  315. if (!dbc->ring_out)
  316. goto out_fail;
  317. /* Allocate and populate ERST: */
  318. ret = xhci_alloc_erst(xhci, dbc->ring_evt, &dbc->erst, flags);
  319. if (ret)
  320. goto erst_fail;
  321. /* Allocate context data structure: */
  322. dbc->ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
  323. if (!dbc->ctx)
  324. goto ctx_fail;
  325. /* Allocate the string table: */
  326. dbc->string_size = sizeof(struct dbc_str_descs);
  327. dbc->string = dbc_dma_alloc_coherent(xhci,
  328. dbc->string_size,
  329. &dbc->string_dma,
  330. flags);
  331. if (!dbc->string)
  332. goto string_fail;
  333. /* Setup ERST register: */
  334. writel(dbc->erst.erst_size, &dbc->regs->ersts);
  335. xhci_write_64(xhci, dbc->erst.erst_dma_addr, &dbc->regs->erstba);
  336. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  337. dbc->ring_evt->dequeue);
  338. xhci_write_64(xhci, deq, &dbc->regs->erdp);
  339. /* Setup strings and contexts: */
  340. string_length = xhci_dbc_populate_strings(dbc->string);
  341. xhci_dbc_init_contexts(xhci, string_length);
  342. mmiowb();
  343. xhci_dbc_eps_init(xhci);
  344. dbc->state = DS_INITIALIZED;
  345. return 0;
  346. string_fail:
  347. xhci_free_container_ctx(xhci, dbc->ctx);
  348. dbc->ctx = NULL;
  349. ctx_fail:
  350. xhci_free_erst(xhci, &dbc->erst);
  351. erst_fail:
  352. xhci_ring_free(xhci, dbc->ring_out);
  353. dbc->ring_out = NULL;
  354. out_fail:
  355. xhci_ring_free(xhci, dbc->ring_in);
  356. dbc->ring_in = NULL;
  357. in_fail:
  358. xhci_ring_free(xhci, dbc->ring_evt);
  359. dbc->ring_evt = NULL;
  360. evt_fail:
  361. return -ENOMEM;
  362. }
  363. static void xhci_dbc_mem_cleanup(struct xhci_hcd *xhci)
  364. {
  365. struct xhci_dbc *dbc = xhci->dbc;
  366. if (!dbc)
  367. return;
  368. xhci_dbc_eps_exit(xhci);
  369. if (dbc->string) {
  370. dbc_dma_free_coherent(xhci,
  371. dbc->string_size,
  372. dbc->string, dbc->string_dma);
  373. dbc->string = NULL;
  374. }
  375. xhci_free_container_ctx(xhci, dbc->ctx);
  376. dbc->ctx = NULL;
  377. xhci_free_erst(xhci, &dbc->erst);
  378. xhci_ring_free(xhci, dbc->ring_out);
  379. xhci_ring_free(xhci, dbc->ring_in);
  380. xhci_ring_free(xhci, dbc->ring_evt);
  381. dbc->ring_in = NULL;
  382. dbc->ring_out = NULL;
  383. dbc->ring_evt = NULL;
  384. }
  385. static int xhci_do_dbc_start(struct xhci_hcd *xhci)
  386. {
  387. int ret;
  388. u32 ctrl;
  389. struct xhci_dbc *dbc = xhci->dbc;
  390. if (dbc->state != DS_DISABLED)
  391. return -EINVAL;
  392. writel(0, &dbc->regs->control);
  393. ret = xhci_handshake(&dbc->regs->control,
  394. DBC_CTRL_DBC_ENABLE,
  395. 0, 1000);
  396. if (ret)
  397. return ret;
  398. ret = xhci_dbc_mem_init(xhci, GFP_ATOMIC);
  399. if (ret)
  400. return ret;
  401. ctrl = readl(&dbc->regs->control);
  402. writel(ctrl | DBC_CTRL_DBC_ENABLE | DBC_CTRL_PORT_ENABLE,
  403. &dbc->regs->control);
  404. ret = xhci_handshake(&dbc->regs->control,
  405. DBC_CTRL_DBC_ENABLE,
  406. DBC_CTRL_DBC_ENABLE, 1000);
  407. if (ret)
  408. return ret;
  409. dbc->state = DS_ENABLED;
  410. return 0;
  411. }
  412. static int xhci_do_dbc_stop(struct xhci_hcd *xhci)
  413. {
  414. struct xhci_dbc *dbc = xhci->dbc;
  415. if (dbc->state == DS_DISABLED)
  416. return -1;
  417. writel(0, &dbc->regs->control);
  418. xhci_dbc_mem_cleanup(xhci);
  419. dbc->state = DS_DISABLED;
  420. return 0;
  421. }
  422. static int xhci_dbc_start(struct xhci_hcd *xhci)
  423. {
  424. int ret;
  425. unsigned long flags;
  426. struct xhci_dbc *dbc = xhci->dbc;
  427. WARN_ON(!dbc);
  428. pm_runtime_get_sync(xhci_to_hcd(xhci)->self.controller);
  429. spin_lock_irqsave(&dbc->lock, flags);
  430. ret = xhci_do_dbc_start(xhci);
  431. spin_unlock_irqrestore(&dbc->lock, flags);
  432. if (ret) {
  433. pm_runtime_put(xhci_to_hcd(xhci)->self.controller);
  434. return ret;
  435. }
  436. return mod_delayed_work(system_wq, &dbc->event_work, 1);
  437. }
  438. static void xhci_dbc_stop(struct xhci_hcd *xhci)
  439. {
  440. int ret;
  441. unsigned long flags;
  442. struct xhci_dbc *dbc = xhci->dbc;
  443. struct dbc_port *port = &dbc->port;
  444. WARN_ON(!dbc);
  445. cancel_delayed_work_sync(&dbc->event_work);
  446. if (port->registered)
  447. xhci_dbc_tty_unregister_device(xhci);
  448. spin_lock_irqsave(&dbc->lock, flags);
  449. ret = xhci_do_dbc_stop(xhci);
  450. spin_unlock_irqrestore(&dbc->lock, flags);
  451. if (!ret)
  452. pm_runtime_put_sync(xhci_to_hcd(xhci)->self.controller);
  453. }
  454. static void
  455. dbc_handle_port_status(struct xhci_hcd *xhci, union xhci_trb *event)
  456. {
  457. u32 portsc;
  458. struct xhci_dbc *dbc = xhci->dbc;
  459. portsc = readl(&dbc->regs->portsc);
  460. if (portsc & DBC_PORTSC_CONN_CHANGE)
  461. xhci_info(xhci, "DbC port connect change\n");
  462. if (portsc & DBC_PORTSC_RESET_CHANGE)
  463. xhci_info(xhci, "DbC port reset change\n");
  464. if (portsc & DBC_PORTSC_LINK_CHANGE)
  465. xhci_info(xhci, "DbC port link status change\n");
  466. if (portsc & DBC_PORTSC_CONFIG_CHANGE)
  467. xhci_info(xhci, "DbC config error change\n");
  468. /* Port reset change bit will be cleared in other place: */
  469. writel(portsc & ~DBC_PORTSC_RESET_CHANGE, &dbc->regs->portsc);
  470. }
  471. static void dbc_handle_xfer_event(struct xhci_hcd *xhci, union xhci_trb *event)
  472. {
  473. struct dbc_ep *dep;
  474. struct xhci_ring *ring;
  475. int ep_id;
  476. int status;
  477. u32 comp_code;
  478. size_t remain_length;
  479. struct dbc_request *req = NULL, *r;
  480. comp_code = GET_COMP_CODE(le32_to_cpu(event->generic.field[2]));
  481. remain_length = EVENT_TRB_LEN(le32_to_cpu(event->generic.field[2]));
  482. ep_id = TRB_TO_EP_ID(le32_to_cpu(event->generic.field[3]));
  483. dep = (ep_id == EPID_OUT) ?
  484. get_out_ep(xhci) : get_in_ep(xhci);
  485. ring = dep->ring;
  486. switch (comp_code) {
  487. case COMP_SUCCESS:
  488. remain_length = 0;
  489. /* FALLTHROUGH */
  490. case COMP_SHORT_PACKET:
  491. status = 0;
  492. break;
  493. case COMP_TRB_ERROR:
  494. case COMP_BABBLE_DETECTED_ERROR:
  495. case COMP_USB_TRANSACTION_ERROR:
  496. case COMP_STALL_ERROR:
  497. xhci_warn(xhci, "tx error %d detected\n", comp_code);
  498. status = -comp_code;
  499. break;
  500. default:
  501. xhci_err(xhci, "unknown tx error %d\n", comp_code);
  502. status = -comp_code;
  503. break;
  504. }
  505. /* Match the pending request: */
  506. list_for_each_entry(r, &dep->list_pending, list_pending) {
  507. if (r->trb_dma == event->trans_event.buffer) {
  508. req = r;
  509. break;
  510. }
  511. }
  512. if (!req) {
  513. xhci_warn(xhci, "no matched request\n");
  514. return;
  515. }
  516. trace_xhci_dbc_handle_transfer(ring, &req->trb->generic);
  517. ring->num_trbs_free++;
  518. req->actual = req->length - remain_length;
  519. xhci_dbc_giveback(req, status);
  520. }
  521. static enum evtreturn xhci_dbc_do_handle_events(struct xhci_dbc *dbc)
  522. {
  523. dma_addr_t deq;
  524. struct dbc_ep *dep;
  525. union xhci_trb *evt;
  526. u32 ctrl, portsc;
  527. struct xhci_hcd *xhci = dbc->xhci;
  528. bool update_erdp = false;
  529. /* DbC state machine: */
  530. switch (dbc->state) {
  531. case DS_DISABLED:
  532. case DS_INITIALIZED:
  533. return EVT_ERR;
  534. case DS_ENABLED:
  535. portsc = readl(&dbc->regs->portsc);
  536. if (portsc & DBC_PORTSC_CONN_STATUS) {
  537. dbc->state = DS_CONNECTED;
  538. xhci_info(xhci, "DbC connected\n");
  539. }
  540. return EVT_DONE;
  541. case DS_CONNECTED:
  542. ctrl = readl(&dbc->regs->control);
  543. if (ctrl & DBC_CTRL_DBC_RUN) {
  544. dbc->state = DS_CONFIGURED;
  545. xhci_info(xhci, "DbC configured\n");
  546. portsc = readl(&dbc->regs->portsc);
  547. writel(portsc, &dbc->regs->portsc);
  548. return EVT_GSER;
  549. }
  550. return EVT_DONE;
  551. case DS_CONFIGURED:
  552. /* Handle cable unplug event: */
  553. portsc = readl(&dbc->regs->portsc);
  554. if (!(portsc & DBC_PORTSC_PORT_ENABLED) &&
  555. !(portsc & DBC_PORTSC_CONN_STATUS)) {
  556. xhci_info(xhci, "DbC cable unplugged\n");
  557. dbc->state = DS_ENABLED;
  558. xhci_dbc_flush_reqests(dbc);
  559. return EVT_DISC;
  560. }
  561. /* Handle debug port reset event: */
  562. if (portsc & DBC_PORTSC_RESET_CHANGE) {
  563. xhci_info(xhci, "DbC port reset\n");
  564. writel(portsc, &dbc->regs->portsc);
  565. dbc->state = DS_ENABLED;
  566. xhci_dbc_flush_reqests(dbc);
  567. return EVT_DISC;
  568. }
  569. /* Handle endpoint stall event: */
  570. ctrl = readl(&dbc->regs->control);
  571. if ((ctrl & DBC_CTRL_HALT_IN_TR) ||
  572. (ctrl & DBC_CTRL_HALT_OUT_TR)) {
  573. xhci_info(xhci, "DbC Endpoint stall\n");
  574. dbc->state = DS_STALLED;
  575. if (ctrl & DBC_CTRL_HALT_IN_TR) {
  576. dep = get_in_ep(xhci);
  577. xhci_dbc_flush_endpoint_requests(dep);
  578. }
  579. if (ctrl & DBC_CTRL_HALT_OUT_TR) {
  580. dep = get_out_ep(xhci);
  581. xhci_dbc_flush_endpoint_requests(dep);
  582. }
  583. return EVT_DONE;
  584. }
  585. /* Clear DbC run change bit: */
  586. if (ctrl & DBC_CTRL_DBC_RUN_CHANGE) {
  587. writel(ctrl, &dbc->regs->control);
  588. ctrl = readl(&dbc->regs->control);
  589. }
  590. break;
  591. case DS_STALLED:
  592. ctrl = readl(&dbc->regs->control);
  593. if (!(ctrl & DBC_CTRL_HALT_IN_TR) &&
  594. !(ctrl & DBC_CTRL_HALT_OUT_TR) &&
  595. (ctrl & DBC_CTRL_DBC_RUN)) {
  596. dbc->state = DS_CONFIGURED;
  597. break;
  598. }
  599. return EVT_DONE;
  600. default:
  601. xhci_err(xhci, "Unknown DbC state %d\n", dbc->state);
  602. break;
  603. }
  604. /* Handle the events in the event ring: */
  605. evt = dbc->ring_evt->dequeue;
  606. while ((le32_to_cpu(evt->event_cmd.flags) & TRB_CYCLE) ==
  607. dbc->ring_evt->cycle_state) {
  608. /*
  609. * Add a barrier between reading the cycle flag and any
  610. * reads of the event's flags/data below:
  611. */
  612. rmb();
  613. trace_xhci_dbc_handle_event(dbc->ring_evt, &evt->generic);
  614. switch (le32_to_cpu(evt->event_cmd.flags) & TRB_TYPE_BITMASK) {
  615. case TRB_TYPE(TRB_PORT_STATUS):
  616. dbc_handle_port_status(xhci, evt);
  617. break;
  618. case TRB_TYPE(TRB_TRANSFER):
  619. dbc_handle_xfer_event(xhci, evt);
  620. break;
  621. default:
  622. break;
  623. }
  624. inc_deq(xhci, dbc->ring_evt);
  625. evt = dbc->ring_evt->dequeue;
  626. update_erdp = true;
  627. }
  628. /* Update event ring dequeue pointer: */
  629. if (update_erdp) {
  630. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  631. dbc->ring_evt->dequeue);
  632. xhci_write_64(xhci, deq, &dbc->regs->erdp);
  633. }
  634. return EVT_DONE;
  635. }
  636. static void xhci_dbc_handle_events(struct work_struct *work)
  637. {
  638. int ret;
  639. enum evtreturn evtr;
  640. struct xhci_dbc *dbc;
  641. unsigned long flags;
  642. struct xhci_hcd *xhci;
  643. dbc = container_of(to_delayed_work(work), struct xhci_dbc, event_work);
  644. xhci = dbc->xhci;
  645. spin_lock_irqsave(&dbc->lock, flags);
  646. evtr = xhci_dbc_do_handle_events(dbc);
  647. spin_unlock_irqrestore(&dbc->lock, flags);
  648. switch (evtr) {
  649. case EVT_GSER:
  650. ret = xhci_dbc_tty_register_device(xhci);
  651. if (ret) {
  652. xhci_err(xhci, "failed to alloc tty device\n");
  653. break;
  654. }
  655. xhci_info(xhci, "DbC now attached to /dev/ttyDBC0\n");
  656. break;
  657. case EVT_DISC:
  658. xhci_dbc_tty_unregister_device(xhci);
  659. break;
  660. case EVT_DONE:
  661. break;
  662. default:
  663. xhci_info(xhci, "stop handling dbc events\n");
  664. return;
  665. }
  666. mod_delayed_work(system_wq, &dbc->event_work, 1);
  667. }
  668. static void xhci_do_dbc_exit(struct xhci_hcd *xhci)
  669. {
  670. unsigned long flags;
  671. spin_lock_irqsave(&xhci->lock, flags);
  672. kfree(xhci->dbc);
  673. xhci->dbc = NULL;
  674. spin_unlock_irqrestore(&xhci->lock, flags);
  675. }
  676. static int xhci_do_dbc_init(struct xhci_hcd *xhci)
  677. {
  678. u32 reg;
  679. struct xhci_dbc *dbc;
  680. unsigned long flags;
  681. void __iomem *base;
  682. int dbc_cap_offs;
  683. base = &xhci->cap_regs->hc_capbase;
  684. dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG);
  685. if (!dbc_cap_offs)
  686. return -ENODEV;
  687. dbc = kzalloc(sizeof(*dbc), GFP_KERNEL);
  688. if (!dbc)
  689. return -ENOMEM;
  690. dbc->regs = base + dbc_cap_offs;
  691. /* We will avoid using DbC in xhci driver if it's in use. */
  692. reg = readl(&dbc->regs->control);
  693. if (reg & DBC_CTRL_DBC_ENABLE) {
  694. kfree(dbc);
  695. return -EBUSY;
  696. }
  697. spin_lock_irqsave(&xhci->lock, flags);
  698. if (xhci->dbc) {
  699. spin_unlock_irqrestore(&xhci->lock, flags);
  700. kfree(dbc);
  701. return -EBUSY;
  702. }
  703. xhci->dbc = dbc;
  704. spin_unlock_irqrestore(&xhci->lock, flags);
  705. dbc->xhci = xhci;
  706. INIT_DELAYED_WORK(&dbc->event_work, xhci_dbc_handle_events);
  707. spin_lock_init(&dbc->lock);
  708. return 0;
  709. }
  710. static ssize_t dbc_show(struct device *dev,
  711. struct device_attribute *attr,
  712. char *buf)
  713. {
  714. const char *p;
  715. struct xhci_dbc *dbc;
  716. struct xhci_hcd *xhci;
  717. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  718. dbc = xhci->dbc;
  719. switch (dbc->state) {
  720. case DS_DISABLED:
  721. p = "disabled";
  722. break;
  723. case DS_INITIALIZED:
  724. p = "initialized";
  725. break;
  726. case DS_ENABLED:
  727. p = "enabled";
  728. break;
  729. case DS_CONNECTED:
  730. p = "connected";
  731. break;
  732. case DS_CONFIGURED:
  733. p = "configured";
  734. break;
  735. case DS_STALLED:
  736. p = "stalled";
  737. break;
  738. default:
  739. p = "unknown";
  740. }
  741. return sprintf(buf, "%s\n", p);
  742. }
  743. static ssize_t dbc_store(struct device *dev,
  744. struct device_attribute *attr,
  745. const char *buf, size_t count)
  746. {
  747. struct xhci_hcd *xhci;
  748. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  749. if (!strncmp(buf, "enable", 6))
  750. xhci_dbc_start(xhci);
  751. else if (!strncmp(buf, "disable", 7))
  752. xhci_dbc_stop(xhci);
  753. else
  754. return -EINVAL;
  755. return count;
  756. }
  757. static DEVICE_ATTR_RW(dbc);
  758. int xhci_dbc_init(struct xhci_hcd *xhci)
  759. {
  760. int ret;
  761. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  762. ret = xhci_do_dbc_init(xhci);
  763. if (ret)
  764. goto init_err3;
  765. ret = xhci_dbc_tty_register_driver(xhci);
  766. if (ret)
  767. goto init_err2;
  768. ret = device_create_file(dev, &dev_attr_dbc);
  769. if (ret)
  770. goto init_err1;
  771. return 0;
  772. init_err1:
  773. xhci_dbc_tty_unregister_driver();
  774. init_err2:
  775. xhci_do_dbc_exit(xhci);
  776. init_err3:
  777. return ret;
  778. }
  779. void xhci_dbc_exit(struct xhci_hcd *xhci)
  780. {
  781. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  782. if (!xhci->dbc)
  783. return;
  784. device_remove_file(dev, &dev_attr_dbc);
  785. xhci_dbc_tty_unregister_driver();
  786. xhci_dbc_stop(xhci);
  787. xhci_do_dbc_exit(xhci);
  788. }
  789. #ifdef CONFIG_PM
  790. int xhci_dbc_suspend(struct xhci_hcd *xhci)
  791. {
  792. struct xhci_dbc *dbc = xhci->dbc;
  793. if (!dbc)
  794. return 0;
  795. if (dbc->state == DS_CONFIGURED)
  796. dbc->resume_required = 1;
  797. xhci_dbc_stop(xhci);
  798. return 0;
  799. }
  800. int xhci_dbc_resume(struct xhci_hcd *xhci)
  801. {
  802. int ret = 0;
  803. struct xhci_dbc *dbc = xhci->dbc;
  804. if (!dbc)
  805. return 0;
  806. if (dbc->resume_required) {
  807. dbc->resume_required = 0;
  808. xhci_dbc_start(xhci);
  809. }
  810. return ret;
  811. }
  812. #endif /* CONFIG_PM */