tsens-8960.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/platform_device.h>
  6. #include <linux/delay.h>
  7. #include <linux/bitops.h>
  8. #include <linux/regmap.h>
  9. #include <linux/thermal.h>
  10. #include "tsens.h"
  11. #define CAL_MDEGC 30000
  12. #define CONFIG_ADDR 0x3640
  13. #define CONFIG_ADDR_8660 0x3620
  14. /* CONFIG_ADDR bitmasks */
  15. #define CONFIG 0x9b
  16. #define CONFIG_MASK 0xf
  17. #define CONFIG_8660 1
  18. #define CONFIG_SHIFT_8660 28
  19. #define CONFIG_MASK_8660 (3 << CONFIG_SHIFT_8660)
  20. #define STATUS_CNTL_ADDR_8064 0x3660
  21. #define CNTL_ADDR 0x3620
  22. /* CNTL_ADDR bitmasks */
  23. #define EN BIT(0)
  24. #define SW_RST BIT(1)
  25. #define SENSOR0_EN BIT(3)
  26. #define SLP_CLK_ENA BIT(26)
  27. #define SLP_CLK_ENA_8660 BIT(24)
  28. #define MEASURE_PERIOD 1
  29. #define SENSOR0_SHIFT 3
  30. /* INT_STATUS_ADDR bitmasks */
  31. #define MIN_STATUS_MASK BIT(0)
  32. #define LOWER_STATUS_CLR BIT(1)
  33. #define UPPER_STATUS_CLR BIT(2)
  34. #define MAX_STATUS_MASK BIT(3)
  35. #define THRESHOLD_ADDR 0x3624
  36. /* THRESHOLD_ADDR bitmasks */
  37. #define THRESHOLD_MAX_LIMIT_SHIFT 24
  38. #define THRESHOLD_MIN_LIMIT_SHIFT 16
  39. #define THRESHOLD_UPPER_LIMIT_SHIFT 8
  40. #define THRESHOLD_LOWER_LIMIT_SHIFT 0
  41. /* Initial temperature threshold values */
  42. #define LOWER_LIMIT_TH 0x50
  43. #define UPPER_LIMIT_TH 0xdf
  44. #define MIN_LIMIT_TH 0x0
  45. #define MAX_LIMIT_TH 0xff
  46. #define S0_STATUS_ADDR 0x3628
  47. #define INT_STATUS_ADDR 0x363c
  48. #define TRDY_MASK BIT(7)
  49. #define TIMEOUT_US 100
  50. static int suspend_8960(struct tsens_device *tmdev)
  51. {
  52. int ret;
  53. unsigned int mask;
  54. struct regmap *map = tmdev->tm_map;
  55. ret = regmap_read(map, THRESHOLD_ADDR, &tmdev->ctx.threshold);
  56. if (ret)
  57. return ret;
  58. ret = regmap_read(map, CNTL_ADDR, &tmdev->ctx.control);
  59. if (ret)
  60. return ret;
  61. if (tmdev->num_sensors > 1)
  62. mask = SLP_CLK_ENA | EN;
  63. else
  64. mask = SLP_CLK_ENA_8660 | EN;
  65. ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
  66. if (ret)
  67. return ret;
  68. return 0;
  69. }
  70. static int resume_8960(struct tsens_device *tmdev)
  71. {
  72. int ret;
  73. struct regmap *map = tmdev->tm_map;
  74. ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
  75. if (ret)
  76. return ret;
  77. /*
  78. * Separate CONFIG restore is not needed only for 8660 as
  79. * config is part of CTRL Addr and its restored as such
  80. */
  81. if (tmdev->num_sensors > 1) {
  82. ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
  83. if (ret)
  84. return ret;
  85. }
  86. ret = regmap_write(map, THRESHOLD_ADDR, tmdev->ctx.threshold);
  87. if (ret)
  88. return ret;
  89. ret = regmap_write(map, CNTL_ADDR, tmdev->ctx.control);
  90. if (ret)
  91. return ret;
  92. return 0;
  93. }
  94. static int enable_8960(struct tsens_device *tmdev, int id)
  95. {
  96. int ret;
  97. u32 reg, mask;
  98. ret = regmap_read(tmdev->tm_map, CNTL_ADDR, &reg);
  99. if (ret)
  100. return ret;
  101. mask = BIT(id + SENSOR0_SHIFT);
  102. ret = regmap_write(tmdev->tm_map, CNTL_ADDR, reg | SW_RST);
  103. if (ret)
  104. return ret;
  105. if (tmdev->num_sensors > 1)
  106. reg |= mask | SLP_CLK_ENA | EN;
  107. else
  108. reg |= mask | SLP_CLK_ENA_8660 | EN;
  109. ret = regmap_write(tmdev->tm_map, CNTL_ADDR, reg);
  110. if (ret)
  111. return ret;
  112. return 0;
  113. }
  114. static void disable_8960(struct tsens_device *tmdev)
  115. {
  116. int ret;
  117. u32 reg_cntl;
  118. u32 mask;
  119. mask = GENMASK(tmdev->num_sensors - 1, 0);
  120. mask <<= SENSOR0_SHIFT;
  121. mask |= EN;
  122. ret = regmap_read(tmdev->tm_map, CNTL_ADDR, &reg_cntl);
  123. if (ret)
  124. return;
  125. reg_cntl &= ~mask;
  126. if (tmdev->num_sensors > 1)
  127. reg_cntl &= ~SLP_CLK_ENA;
  128. else
  129. reg_cntl &= ~SLP_CLK_ENA_8660;
  130. regmap_write(tmdev->tm_map, CNTL_ADDR, reg_cntl);
  131. }
  132. static int init_8960(struct tsens_device *tmdev)
  133. {
  134. int ret, i;
  135. u32 reg_cntl;
  136. tmdev->tm_map = dev_get_regmap(tmdev->dev, NULL);
  137. if (!tmdev->tm_map)
  138. return -ENODEV;
  139. /*
  140. * The status registers for each sensor are discontiguous
  141. * because some SoCs have 5 sensors while others have more
  142. * but the control registers stay in the same place, i.e
  143. * directly after the first 5 status registers.
  144. */
  145. for (i = 0; i < tmdev->num_sensors; i++) {
  146. if (i >= 5)
  147. tmdev->sensor[i].status = S0_STATUS_ADDR + 40;
  148. tmdev->sensor[i].status += i * 4;
  149. }
  150. reg_cntl = SW_RST;
  151. ret = regmap_update_bits(tmdev->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
  152. if (ret)
  153. return ret;
  154. if (tmdev->num_sensors > 1) {
  155. reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
  156. reg_cntl &= ~SW_RST;
  157. ret = regmap_update_bits(tmdev->tm_map, CONFIG_ADDR,
  158. CONFIG_MASK, CONFIG);
  159. } else {
  160. reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16);
  161. reg_cntl &= ~CONFIG_MASK_8660;
  162. reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660;
  163. }
  164. reg_cntl |= GENMASK(tmdev->num_sensors - 1, 0) << SENSOR0_SHIFT;
  165. ret = regmap_write(tmdev->tm_map, CNTL_ADDR, reg_cntl);
  166. if (ret)
  167. return ret;
  168. reg_cntl |= EN;
  169. ret = regmap_write(tmdev->tm_map, CNTL_ADDR, reg_cntl);
  170. if (ret)
  171. return ret;
  172. return 0;
  173. }
  174. static int calibrate_8960(struct tsens_device *tmdev)
  175. {
  176. int i;
  177. char *data;
  178. ssize_t num_read = tmdev->num_sensors;
  179. struct tsens_sensor *s = tmdev->sensor;
  180. data = qfprom_read(tmdev->dev, "calib");
  181. if (IS_ERR(data))
  182. data = qfprom_read(tmdev->dev, "calib_backup");
  183. if (IS_ERR(data))
  184. return PTR_ERR(data);
  185. for (i = 0; i < num_read; i++, s++)
  186. s->offset = data[i];
  187. return 0;
  188. }
  189. /* Temperature on y axis and ADC-code on x-axis */
  190. static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s)
  191. {
  192. int slope, offset;
  193. slope = thermal_zone_get_slope(s->tzd);
  194. offset = CAL_MDEGC - slope * s->offset;
  195. return adc_code * slope + offset;
  196. }
  197. static int get_temp_8960(struct tsens_device *tmdev, int id, int *temp)
  198. {
  199. int ret;
  200. u32 code, trdy;
  201. const struct tsens_sensor *s = &tmdev->sensor[id];
  202. unsigned long timeout;
  203. timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
  204. do {
  205. ret = regmap_read(tmdev->tm_map, INT_STATUS_ADDR, &trdy);
  206. if (ret)
  207. return ret;
  208. if (!(trdy & TRDY_MASK))
  209. continue;
  210. ret = regmap_read(tmdev->tm_map, s->status, &code);
  211. if (ret)
  212. return ret;
  213. *temp = code_to_mdegC(code, s);
  214. return 0;
  215. } while (time_before(jiffies, timeout));
  216. return -ETIMEDOUT;
  217. }
  218. static const struct tsens_ops ops_8960 = {
  219. .init = init_8960,
  220. .calibrate = calibrate_8960,
  221. .get_temp = get_temp_8960,
  222. .enable = enable_8960,
  223. .disable = disable_8960,
  224. .suspend = suspend_8960,
  225. .resume = resume_8960,
  226. };
  227. const struct tsens_data data_8960 = {
  228. .num_sensors = 11,
  229. .ops = &ops_8960,
  230. };