stpmic1_regulator.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) STMicroelectronics 2018
  3. // Author: Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
  4. #include <linux/interrupt.h>
  5. #include <linux/mfd/stpmic1.h>
  6. #include <linux/module.h>
  7. #include <linux/of_irq.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/regmap.h>
  10. #include <linux/regulator/driver.h>
  11. #include <linux/regulator/machine.h>
  12. #include <linux/regulator/of_regulator.h>
  13. /**
  14. * stpmic1 regulator description
  15. * @desc: regulator framework description
  16. * @mask_reset_reg: mask reset register address
  17. * @mask_reset_mask: mask rank and mask reset register mask
  18. * @icc_reg: icc register address
  19. * @icc_mask: icc register mask
  20. */
  21. struct stpmic1_regulator_cfg {
  22. struct regulator_desc desc;
  23. u8 mask_reset_reg;
  24. u8 mask_reset_mask;
  25. u8 icc_reg;
  26. u8 icc_mask;
  27. };
  28. /**
  29. * stpmic1 regulator data: this structure is used as driver data
  30. * @regul_id: regulator id
  31. * @reg_node: DT node of regulator (unused on non-DT platforms)
  32. * @cfg: stpmic specific regulator description
  33. * @mask_reset: mask_reset bit value
  34. * @irq_curlim: current limit interrupt number
  35. * @regmap: point to parent regmap structure
  36. */
  37. struct stpmic1_regulator {
  38. unsigned int regul_id;
  39. struct device_node *reg_node;
  40. struct stpmic1_regulator_cfg *cfg;
  41. u8 mask_reset;
  42. int irq_curlim;
  43. struct regmap *regmap;
  44. };
  45. static int stpmic1_set_mode(struct regulator_dev *rdev, unsigned int mode);
  46. static unsigned int stpmic1_get_mode(struct regulator_dev *rdev);
  47. static int stpmic1_set_icc(struct regulator_dev *rdev);
  48. static int stpmic1_regulator_parse_dt(void *driver_data);
  49. static unsigned int stpmic1_map_mode(unsigned int mode);
  50. enum {
  51. STPMIC1_BUCK1 = 0,
  52. STPMIC1_BUCK2 = 1,
  53. STPMIC1_BUCK3 = 2,
  54. STPMIC1_BUCK4 = 3,
  55. STPMIC1_LDO1 = 4,
  56. STPMIC1_LDO2 = 5,
  57. STPMIC1_LDO3 = 6,
  58. STPMIC1_LDO4 = 7,
  59. STPMIC1_LDO5 = 8,
  60. STPMIC1_LDO6 = 9,
  61. STPMIC1_VREF_DDR = 10,
  62. STPMIC1_BOOST = 11,
  63. STPMIC1_VBUS_OTG = 12,
  64. STPMIC1_SW_OUT = 13,
  65. };
  66. /* Enable time worst case is 5000mV/(2250uV/uS) */
  67. #define PMIC_ENABLE_TIME_US 2200
  68. #define STPMIC1_BUCK_MODE_NORMAL 0
  69. #define STPMIC1_BUCK_MODE_LP BUCK_HPLP_ENABLE_MASK
  70. struct regulator_linear_range buck1_ranges[] = {
  71. REGULATOR_LINEAR_RANGE(600000, 0, 30, 25000),
  72. REGULATOR_LINEAR_RANGE(1350000, 31, 63, 0),
  73. };
  74. struct regulator_linear_range buck2_ranges[] = {
  75. REGULATOR_LINEAR_RANGE(1000000, 0, 17, 0),
  76. REGULATOR_LINEAR_RANGE(1050000, 18, 19, 0),
  77. REGULATOR_LINEAR_RANGE(1100000, 20, 21, 0),
  78. REGULATOR_LINEAR_RANGE(1150000, 22, 23, 0),
  79. REGULATOR_LINEAR_RANGE(1200000, 24, 25, 0),
  80. REGULATOR_LINEAR_RANGE(1250000, 26, 27, 0),
  81. REGULATOR_LINEAR_RANGE(1300000, 28, 29, 0),
  82. REGULATOR_LINEAR_RANGE(1350000, 30, 31, 0),
  83. REGULATOR_LINEAR_RANGE(1400000, 32, 33, 0),
  84. REGULATOR_LINEAR_RANGE(1450000, 34, 35, 0),
  85. REGULATOR_LINEAR_RANGE(1500000, 36, 63, 0),
  86. };
  87. struct regulator_linear_range buck3_ranges[] = {
  88. REGULATOR_LINEAR_RANGE(1000000, 0, 19, 0),
  89. REGULATOR_LINEAR_RANGE(1100000, 20, 23, 0),
  90. REGULATOR_LINEAR_RANGE(1200000, 24, 27, 0),
  91. REGULATOR_LINEAR_RANGE(1300000, 28, 31, 0),
  92. REGULATOR_LINEAR_RANGE(1400000, 32, 35, 0),
  93. REGULATOR_LINEAR_RANGE(1500000, 36, 55, 100000),
  94. REGULATOR_LINEAR_RANGE(3400000, 56, 63, 0),
  95. };
  96. struct regulator_linear_range buck4_ranges[] = {
  97. REGULATOR_LINEAR_RANGE(600000, 0, 27, 25000),
  98. REGULATOR_LINEAR_RANGE(1300000, 28, 29, 0),
  99. REGULATOR_LINEAR_RANGE(1350000, 30, 31, 0),
  100. REGULATOR_LINEAR_RANGE(1400000, 32, 33, 0),
  101. REGULATOR_LINEAR_RANGE(1450000, 34, 35, 0),
  102. REGULATOR_LINEAR_RANGE(1500000, 36, 60, 100000),
  103. REGULATOR_LINEAR_RANGE(3900000, 61, 63, 0),
  104. };
  105. struct regulator_linear_range ldo1_ranges[] = {
  106. REGULATOR_LINEAR_RANGE(1700000, 0, 7, 0),
  107. REGULATOR_LINEAR_RANGE(1700000, 8, 24, 100000),
  108. REGULATOR_LINEAR_RANGE(3300000, 25, 31, 0),
  109. };
  110. struct regulator_linear_range ldo2_ranges[] = {
  111. REGULATOR_LINEAR_RANGE(1700000, 0, 7, 0),
  112. REGULATOR_LINEAR_RANGE(1700000, 8, 24, 100000),
  113. REGULATOR_LINEAR_RANGE(3300000, 25, 30, 0),
  114. };
  115. struct regulator_linear_range ldo3_ranges[] = {
  116. REGULATOR_LINEAR_RANGE(1700000, 0, 7, 0),
  117. REGULATOR_LINEAR_RANGE(1700000, 8, 24, 100000),
  118. REGULATOR_LINEAR_RANGE(3300000, 25, 30, 0),
  119. /* with index 31 LDO3 is in DDR mode */
  120. REGULATOR_LINEAR_RANGE(500000, 31, 31, 0),
  121. };
  122. struct regulator_linear_range ldo5_ranges[] = {
  123. REGULATOR_LINEAR_RANGE(1700000, 0, 7, 0),
  124. REGULATOR_LINEAR_RANGE(1700000, 8, 30, 100000),
  125. REGULATOR_LINEAR_RANGE(3900000, 31, 31, 0),
  126. };
  127. struct regulator_linear_range ldo6_ranges[] = {
  128. REGULATOR_LINEAR_RANGE(900000, 0, 24, 100000),
  129. REGULATOR_LINEAR_RANGE(3300000, 25, 31, 0),
  130. };
  131. static struct regulator_ops stpmic1_ldo_ops = {
  132. .list_voltage = regulator_list_voltage_linear_range,
  133. .map_voltage = regulator_map_voltage_linear_range,
  134. .is_enabled = regulator_is_enabled_regmap,
  135. .enable = regulator_enable_regmap,
  136. .disable = regulator_disable_regmap,
  137. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  138. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  139. .set_pull_down = regulator_set_pull_down_regmap,
  140. .set_over_current_protection = stpmic1_set_icc,
  141. };
  142. static struct regulator_ops stpmic1_ldo3_ops = {
  143. .list_voltage = regulator_list_voltage_linear_range,
  144. .map_voltage = regulator_map_voltage_iterate,
  145. .is_enabled = regulator_is_enabled_regmap,
  146. .enable = regulator_enable_regmap,
  147. .disable = regulator_disable_regmap,
  148. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  149. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  150. .set_pull_down = regulator_set_pull_down_regmap,
  151. .get_bypass = regulator_get_bypass_regmap,
  152. .set_bypass = regulator_set_bypass_regmap,
  153. .set_over_current_protection = stpmic1_set_icc,
  154. };
  155. static struct regulator_ops stpmic1_ldo4_fixed_regul_ops = {
  156. .is_enabled = regulator_is_enabled_regmap,
  157. .enable = regulator_enable_regmap,
  158. .disable = regulator_disable_regmap,
  159. .set_pull_down = regulator_set_pull_down_regmap,
  160. .set_over_current_protection = stpmic1_set_icc,
  161. };
  162. static struct regulator_ops stpmic1_buck_ops = {
  163. .list_voltage = regulator_list_voltage_linear_range,
  164. .map_voltage = regulator_map_voltage_linear_range,
  165. .is_enabled = regulator_is_enabled_regmap,
  166. .enable = regulator_enable_regmap,
  167. .disable = regulator_disable_regmap,
  168. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  169. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  170. .set_pull_down = regulator_set_pull_down_regmap,
  171. .set_mode = stpmic1_set_mode,
  172. .get_mode = stpmic1_get_mode,
  173. .set_over_current_protection = stpmic1_set_icc,
  174. };
  175. static struct regulator_ops stpmic1_vref_ddr_ops = {
  176. .is_enabled = regulator_is_enabled_regmap,
  177. .enable = regulator_enable_regmap,
  178. .disable = regulator_disable_regmap,
  179. .set_pull_down = regulator_set_pull_down_regmap,
  180. };
  181. static struct regulator_ops stpmic1_switch_regul_ops = {
  182. .is_enabled = regulator_is_enabled_regmap,
  183. .enable = regulator_enable_regmap,
  184. .disable = regulator_disable_regmap,
  185. .set_over_current_protection = stpmic1_set_icc,
  186. };
  187. #define REG_LDO(ids, base) { \
  188. .name = #ids, \
  189. .id = STPMIC1_##ids, \
  190. .n_voltages = 32, \
  191. .ops = &stpmic1_ldo_ops, \
  192. .linear_ranges = base ## _ranges, \
  193. .n_linear_ranges = ARRAY_SIZE(base ## _ranges), \
  194. .type = REGULATOR_VOLTAGE, \
  195. .owner = THIS_MODULE, \
  196. .vsel_reg = ids##_ACTIVE_CR, \
  197. .vsel_mask = LDO_VOLTAGE_MASK, \
  198. .enable_reg = ids##_ACTIVE_CR, \
  199. .enable_mask = LDO_ENABLE_MASK, \
  200. .enable_val = 1, \
  201. .disable_val = 0, \
  202. .enable_time = PMIC_ENABLE_TIME_US, \
  203. .pull_down_reg = ids##_PULL_DOWN_REG, \
  204. .pull_down_mask = ids##_PULL_DOWN_MASK, \
  205. .supply_name = #base, \
  206. }
  207. #define REG_LDO3(ids, base) { \
  208. .name = #ids, \
  209. .id = STPMIC1_##ids, \
  210. .n_voltages = 32, \
  211. .ops = &stpmic1_ldo3_ops, \
  212. .linear_ranges = ldo3_ranges, \
  213. .n_linear_ranges = ARRAY_SIZE(ldo3_ranges), \
  214. .type = REGULATOR_VOLTAGE, \
  215. .owner = THIS_MODULE, \
  216. .vsel_reg = LDO3_ACTIVE_CR, \
  217. .vsel_mask = LDO_VOLTAGE_MASK, \
  218. .enable_reg = LDO3_ACTIVE_CR, \
  219. .enable_mask = LDO_ENABLE_MASK, \
  220. .enable_val = 1, \
  221. .disable_val = 0, \
  222. .enable_time = PMIC_ENABLE_TIME_US, \
  223. .bypass_reg = LDO3_ACTIVE_CR, \
  224. .bypass_mask = LDO_BYPASS_MASK, \
  225. .bypass_val_on = LDO_BYPASS_MASK, \
  226. .bypass_val_off = 0, \
  227. .pull_down_reg = ids##_PULL_DOWN_REG, \
  228. .pull_down_mask = ids##_PULL_DOWN_MASK, \
  229. .supply_name = #base, \
  230. }
  231. #define REG_LDO4(ids, base) { \
  232. .name = #ids, \
  233. .id = STPMIC1_##ids, \
  234. .n_voltages = 1, \
  235. .ops = &stpmic1_ldo4_fixed_regul_ops, \
  236. .type = REGULATOR_VOLTAGE, \
  237. .owner = THIS_MODULE, \
  238. .min_uV = 3300000, \
  239. .fixed_uV = 3300000, \
  240. .enable_reg = LDO4_ACTIVE_CR, \
  241. .enable_mask = LDO_ENABLE_MASK, \
  242. .enable_val = 1, \
  243. .disable_val = 0, \
  244. .enable_time = PMIC_ENABLE_TIME_US, \
  245. .pull_down_reg = ids##_PULL_DOWN_REG, \
  246. .pull_down_mask = ids##_PULL_DOWN_MASK, \
  247. .supply_name = #base, \
  248. }
  249. #define REG_BUCK(ids, base) { \
  250. .name = #ids, \
  251. .id = STPMIC1_##ids, \
  252. .ops = &stpmic1_buck_ops, \
  253. .n_voltages = 64, \
  254. .linear_ranges = base ## _ranges, \
  255. .n_linear_ranges = ARRAY_SIZE(base ## _ranges), \
  256. .type = REGULATOR_VOLTAGE, \
  257. .owner = THIS_MODULE, \
  258. .vsel_reg = ids##_ACTIVE_CR, \
  259. .vsel_mask = BUCK_VOLTAGE_MASK, \
  260. .enable_reg = ids##_ACTIVE_CR, \
  261. .enable_mask = BUCK_ENABLE_MASK, \
  262. .enable_val = 1, \
  263. .disable_val = 0, \
  264. .enable_time = PMIC_ENABLE_TIME_US, \
  265. .of_map_mode = stpmic1_map_mode, \
  266. .pull_down_reg = ids##_PULL_DOWN_REG, \
  267. .pull_down_mask = ids##_PULL_DOWN_MASK, \
  268. .supply_name = #base, \
  269. }
  270. #define REG_VREF_DDR(ids, base) { \
  271. .name = #ids, \
  272. .id = STPMIC1_##ids, \
  273. .n_voltages = 1, \
  274. .ops = &stpmic1_vref_ddr_ops, \
  275. .type = REGULATOR_VOLTAGE, \
  276. .owner = THIS_MODULE, \
  277. .min_uV = 500000, \
  278. .fixed_uV = 500000, \
  279. .enable_reg = VREF_DDR_ACTIVE_CR, \
  280. .enable_mask = BUCK_ENABLE_MASK, \
  281. .enable_val = 1, \
  282. .disable_val = 0, \
  283. .enable_time = PMIC_ENABLE_TIME_US, \
  284. .pull_down_reg = ids##_PULL_DOWN_REG, \
  285. .pull_down_mask = ids##_PULL_DOWN_MASK, \
  286. .supply_name = #base, \
  287. }
  288. #define REG_SWITCH(ids, base, reg, mask, val) { \
  289. .name = #ids, \
  290. .id = STPMIC1_##ids, \
  291. .n_voltages = 1, \
  292. .ops = &stpmic1_switch_regul_ops, \
  293. .type = REGULATOR_VOLTAGE, \
  294. .owner = THIS_MODULE, \
  295. .min_uV = 0, \
  296. .fixed_uV = 5000000, \
  297. .enable_reg = (reg), \
  298. .enable_mask = (mask), \
  299. .enable_val = (val), \
  300. .disable_val = 0, \
  301. .enable_time = PMIC_ENABLE_TIME_US, \
  302. .supply_name = #base, \
  303. }
  304. struct stpmic1_regulator_cfg stpmic1_regulator_cfgs[] = {
  305. [STPMIC1_BUCK1] = {
  306. .desc = REG_BUCK(BUCK1, buck1),
  307. .icc_reg = BUCKS_ICCTO_CR,
  308. .icc_mask = BIT(0),
  309. .mask_reset_reg = BUCKS_MASK_RESET_CR,
  310. .mask_reset_mask = BIT(0),
  311. },
  312. [STPMIC1_BUCK2] = {
  313. .desc = REG_BUCK(BUCK2, buck2),
  314. .icc_reg = BUCKS_ICCTO_CR,
  315. .icc_mask = BIT(1),
  316. .mask_reset_reg = BUCKS_MASK_RESET_CR,
  317. .mask_reset_mask = BIT(1),
  318. },
  319. [STPMIC1_BUCK3] = {
  320. .desc = REG_BUCK(BUCK3, buck3),
  321. .icc_reg = BUCKS_ICCTO_CR,
  322. .icc_mask = BIT(2),
  323. .mask_reset_reg = BUCKS_MASK_RESET_CR,
  324. .mask_reset_mask = BIT(2),
  325. },
  326. [STPMIC1_BUCK4] = {
  327. .desc = REG_BUCK(BUCK4, buck4),
  328. .icc_reg = BUCKS_ICCTO_CR,
  329. .icc_mask = BIT(3),
  330. .mask_reset_reg = BUCKS_MASK_RESET_CR,
  331. .mask_reset_mask = BIT(3),
  332. },
  333. [STPMIC1_LDO1] = {
  334. .desc = REG_LDO(LDO1, ldo1),
  335. .icc_reg = LDOS_ICCTO_CR,
  336. .icc_mask = BIT(0),
  337. .mask_reset_reg = LDOS_MASK_RESET_CR,
  338. .mask_reset_mask = BIT(0),
  339. },
  340. [STPMIC1_LDO2] = {
  341. .desc = REG_LDO(LDO2, ldo2),
  342. .icc_reg = LDOS_ICCTO_CR,
  343. .icc_mask = BIT(1),
  344. .mask_reset_reg = LDOS_MASK_RESET_CR,
  345. .mask_reset_mask = BIT(1),
  346. },
  347. [STPMIC1_LDO3] = {
  348. .desc = REG_LDO3(LDO3, ldo3),
  349. .icc_reg = LDOS_ICCTO_CR,
  350. .icc_mask = BIT(2),
  351. .mask_reset_reg = LDOS_MASK_RESET_CR,
  352. .mask_reset_mask = BIT(2),
  353. },
  354. [STPMIC1_LDO4] = {
  355. .desc = REG_LDO4(LDO4, ldo4),
  356. .icc_reg = LDOS_ICCTO_CR,
  357. .icc_mask = BIT(3),
  358. .mask_reset_reg = LDOS_MASK_RESET_CR,
  359. .mask_reset_mask = BIT(3),
  360. },
  361. [STPMIC1_LDO5] = {
  362. .desc = REG_LDO(LDO5, ldo5),
  363. .icc_reg = LDOS_ICCTO_CR,
  364. .icc_mask = BIT(4),
  365. .mask_reset_reg = LDOS_MASK_RESET_CR,
  366. .mask_reset_mask = BIT(4),
  367. },
  368. [STPMIC1_LDO6] = {
  369. .desc = REG_LDO(LDO6, ldo6),
  370. .icc_reg = LDOS_ICCTO_CR,
  371. .icc_mask = BIT(5),
  372. .mask_reset_reg = LDOS_MASK_RESET_CR,
  373. .mask_reset_mask = BIT(5),
  374. },
  375. [STPMIC1_VREF_DDR] = {
  376. .desc = REG_VREF_DDR(VREF_DDR, vref_ddr),
  377. .mask_reset_reg = LDOS_MASK_RESET_CR,
  378. .mask_reset_mask = BIT(6),
  379. },
  380. [STPMIC1_BOOST] = {
  381. .desc = REG_SWITCH(BOOST, boost, BST_SW_CR,
  382. BOOST_ENABLED,
  383. BOOST_ENABLED),
  384. .icc_reg = BUCKS_ICCTO_CR,
  385. .icc_mask = BIT(6),
  386. },
  387. [STPMIC1_VBUS_OTG] = {
  388. .desc = REG_SWITCH(VBUS_OTG, pwr_sw1, BST_SW_CR,
  389. USBSW_OTG_SWITCH_ENABLED,
  390. USBSW_OTG_SWITCH_ENABLED),
  391. .icc_reg = BUCKS_ICCTO_CR,
  392. .icc_mask = BIT(4),
  393. },
  394. [STPMIC1_SW_OUT] = {
  395. .desc = REG_SWITCH(SW_OUT, pwr_sw2, BST_SW_CR,
  396. SWIN_SWOUT_ENABLED,
  397. SWIN_SWOUT_ENABLED),
  398. .icc_reg = BUCKS_ICCTO_CR,
  399. .icc_mask = BIT(5),
  400. },
  401. };
  402. static unsigned int stpmic1_map_mode(unsigned int mode)
  403. {
  404. switch (mode) {
  405. case STPMIC1_BUCK_MODE_NORMAL:
  406. return REGULATOR_MODE_NORMAL;
  407. case STPMIC1_BUCK_MODE_LP:
  408. return REGULATOR_MODE_STANDBY;
  409. default:
  410. return REGULATOR_MODE_INVALID;
  411. }
  412. }
  413. static unsigned int stpmic1_get_mode(struct regulator_dev *rdev)
  414. {
  415. int value;
  416. regmap_read(rdev->regmap, rdev->desc->enable_reg, &value);
  417. if (value & STPMIC1_BUCK_MODE_LP)
  418. return REGULATOR_MODE_STANDBY;
  419. return REGULATOR_MODE_NORMAL;
  420. }
  421. static int stpmic1_set_mode(struct regulator_dev *rdev, unsigned int mode)
  422. {
  423. int value;
  424. switch (mode) {
  425. case REGULATOR_MODE_NORMAL:
  426. value = STPMIC1_BUCK_MODE_NORMAL;
  427. break;
  428. case REGULATOR_MODE_STANDBY:
  429. value = STPMIC1_BUCK_MODE_LP;
  430. break;
  431. default:
  432. return -EINVAL;
  433. }
  434. return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
  435. STPMIC1_BUCK_MODE_LP, value);
  436. }
  437. static int stpmic1_set_icc(struct regulator_dev *rdev)
  438. {
  439. struct stpmic1_regulator *regul = rdev_get_drvdata(rdev);
  440. /* enable switch off in case of over current */
  441. return regmap_update_bits(regul->regmap, regul->cfg->icc_reg,
  442. regul->cfg->icc_mask, regul->cfg->icc_mask);
  443. }
  444. static irqreturn_t stpmic1_curlim_irq_handler(int irq, void *data)
  445. {
  446. struct regulator_dev *rdev = (struct regulator_dev *)data;
  447. mutex_lock(&rdev->mutex);
  448. /* Send an overcurrent notification */
  449. regulator_notifier_call_chain(rdev,
  450. REGULATOR_EVENT_OVER_CURRENT,
  451. NULL);
  452. mutex_unlock(&rdev->mutex);
  453. return IRQ_HANDLED;
  454. }
  455. static int stpmic1_regulator_init(struct platform_device *pdev,
  456. struct regulator_dev *rdev)
  457. {
  458. struct stpmic1_regulator *regul = rdev_get_drvdata(rdev);
  459. int ret = 0;
  460. /* set mask reset */
  461. if (regul->mask_reset && regul->cfg->mask_reset_reg != 0) {
  462. ret = regmap_update_bits(regul->regmap,
  463. regul->cfg->mask_reset_reg,
  464. regul->cfg->mask_reset_mask,
  465. regul->cfg->mask_reset_mask);
  466. if (ret) {
  467. dev_err(&pdev->dev, "set mask reset failed\n");
  468. return ret;
  469. }
  470. }
  471. /* setup an irq handler for over-current detection */
  472. if (regul->irq_curlim > 0) {
  473. ret = devm_request_threaded_irq(&pdev->dev,
  474. regul->irq_curlim, NULL,
  475. stpmic1_curlim_irq_handler,
  476. IRQF_ONESHOT | IRQF_SHARED,
  477. pdev->name, rdev);
  478. if (ret) {
  479. dev_err(&pdev->dev, "Request IRQ failed\n");
  480. return ret;
  481. }
  482. }
  483. return 0;
  484. }
  485. #define MATCH(_name, _id) \
  486. [STPMIC1_##_id] = { \
  487. .name = #_name, \
  488. .desc = &stpmic1_regulator_cfgs[STPMIC1_##_id].desc, \
  489. }
  490. static struct of_regulator_match stpmic1_regulators_matches[] = {
  491. MATCH(buck1, BUCK1),
  492. MATCH(buck2, BUCK2),
  493. MATCH(buck3, BUCK3),
  494. MATCH(buck4, BUCK4),
  495. MATCH(ldo1, LDO1),
  496. MATCH(ldo2, LDO2),
  497. MATCH(ldo3, LDO3),
  498. MATCH(ldo4, LDO4),
  499. MATCH(ldo5, LDO5),
  500. MATCH(ldo6, LDO6),
  501. MATCH(vref_ddr, VREF_DDR),
  502. MATCH(boost, BOOST),
  503. MATCH(pwr_sw1, VBUS_OTG),
  504. MATCH(pwr_sw2, SW_OUT),
  505. };
  506. static int stpmic1_regulator_parse_dt(void *driver_data)
  507. {
  508. struct stpmic1_regulator *regul =
  509. (struct stpmic1_regulator *)driver_data;
  510. if (!regul)
  511. return -EINVAL;
  512. if (of_get_property(regul->reg_node, "st,mask-reset", NULL))
  513. regul->mask_reset = 1;
  514. regul->irq_curlim = of_irq_get(regul->reg_node, 0);
  515. return 0;
  516. }
  517. static struct
  518. regulator_dev *stpmic1_regulator_register(struct platform_device *pdev, int id,
  519. struct regulator_init_data *init_data,
  520. struct stpmic1_regulator *regul)
  521. {
  522. struct stpmic1 *pmic_dev = dev_get_drvdata(pdev->dev.parent);
  523. struct regulator_dev *rdev;
  524. struct regulator_config config = {};
  525. config.dev = &pdev->dev;
  526. config.init_data = init_data;
  527. config.of_node = stpmic1_regulators_matches[id].of_node;
  528. config.regmap = pmic_dev->regmap;
  529. config.driver_data = regul;
  530. regul->regul_id = id;
  531. regul->reg_node = config.of_node;
  532. regul->cfg = &stpmic1_regulator_cfgs[id];
  533. regul->regmap = pmic_dev->regmap;
  534. rdev = devm_regulator_register(&pdev->dev, &regul->cfg->desc, &config);
  535. if (IS_ERR(rdev)) {
  536. dev_err(&pdev->dev, "failed to register %s regulator\n",
  537. regul->cfg->desc.name);
  538. }
  539. return rdev;
  540. }
  541. static int stpmic1_regulator_probe(struct platform_device *pdev)
  542. {
  543. struct regulator_dev *rdev;
  544. struct stpmic1_regulator *regul;
  545. struct regulator_init_data *init_data;
  546. struct device_node *np;
  547. int i, ret;
  548. np = pdev->dev.of_node;
  549. ret = of_regulator_match(&pdev->dev, np,
  550. stpmic1_regulators_matches,
  551. ARRAY_SIZE(stpmic1_regulators_matches));
  552. if (ret < 0) {
  553. dev_err(&pdev->dev,
  554. "Error in PMIC regulator device tree node");
  555. return ret;
  556. }
  557. regul = devm_kzalloc(&pdev->dev, ARRAY_SIZE(stpmic1_regulator_cfgs) *
  558. sizeof(struct stpmic1_regulator),
  559. GFP_KERNEL);
  560. if (!regul)
  561. return -ENOMEM;
  562. for (i = 0; i < ARRAY_SIZE(stpmic1_regulator_cfgs); i++) {
  563. /* Parse DT & find regulators to register */
  564. init_data = stpmic1_regulators_matches[i].init_data;
  565. if (init_data)
  566. init_data->regulator_init = &stpmic1_regulator_parse_dt;
  567. rdev = stpmic1_regulator_register(pdev, i, init_data, regul);
  568. if (IS_ERR(rdev))
  569. return PTR_ERR(rdev);
  570. ret = stpmic1_regulator_init(pdev, rdev);
  571. if (ret) {
  572. dev_err(&pdev->dev,
  573. "failed to initialize regulator %d\n", ret);
  574. return ret;
  575. }
  576. regul++;
  577. }
  578. dev_dbg(&pdev->dev, "stpmic1_regulator driver probed\n");
  579. return 0;
  580. }
  581. static const struct of_device_id of_pmic_regulator_match[] = {
  582. { .compatible = "st,stpmic1-regulators" },
  583. { },
  584. };
  585. MODULE_DEVICE_TABLE(of, of_pmic_regulator_match);
  586. static struct platform_driver stpmic1_regulator_driver = {
  587. .driver = {
  588. .name = "stpmic1-regulator",
  589. .of_match_table = of_match_ptr(of_pmic_regulator_match),
  590. },
  591. .probe = stpmic1_regulator_probe,
  592. };
  593. module_platform_driver(stpmic1_regulator_driver);
  594. MODULE_DESCRIPTION("STPMIC1 PMIC voltage regulator driver");
  595. MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
  596. MODULE_LICENSE("GPL v2");