portdrv_pci.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Purpose: PCI Express Port Bus Driver
  4. * Author: Tom Nguyen <tom.l.nguyen@intel.com>
  5. *
  6. * Copyright (C) 2004 Intel
  7. * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
  8. */
  9. #include <linux/pci.h>
  10. #include <linux/kernel.h>
  11. #include <linux/errno.h>
  12. #include <linux/pm.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/init.h>
  15. #include <linux/aer.h>
  16. #include <linux/dmi.h>
  17. #include "../pci.h"
  18. #include "portdrv.h"
  19. /* If this switch is set, PCIe port native services should not be enabled. */
  20. bool pcie_ports_disabled;
  21. /*
  22. * If the user specified "pcie_ports=native", use the PCIe services regardless
  23. * of whether the platform has given us permission. On ACPI systems, this
  24. * means we ignore _OSC.
  25. */
  26. bool pcie_ports_native;
  27. static int __init pcie_port_setup(char *str)
  28. {
  29. if (!strncmp(str, "compat", 6))
  30. pcie_ports_disabled = true;
  31. else if (!strncmp(str, "native", 6))
  32. pcie_ports_native = true;
  33. return 1;
  34. }
  35. __setup("pcie_ports=", pcie_port_setup);
  36. /* global data */
  37. #ifdef CONFIG_PM
  38. static int pcie_port_runtime_suspend(struct device *dev)
  39. {
  40. if (!to_pci_dev(dev)->bridge_d3)
  41. return -EBUSY;
  42. return pcie_port_device_runtime_suspend(dev);
  43. }
  44. static int pcie_port_runtime_idle(struct device *dev)
  45. {
  46. /*
  47. * Assume the PCI core has set bridge_d3 whenever it thinks the port
  48. * should be good to go to D3. Everything else, including moving
  49. * the port to D3, is handled by the PCI core.
  50. */
  51. return to_pci_dev(dev)->bridge_d3 ? 0 : -EBUSY;
  52. }
  53. static const struct dev_pm_ops pcie_portdrv_pm_ops = {
  54. .suspend = pcie_port_device_suspend,
  55. .resume_noirq = pcie_port_device_resume_noirq,
  56. .resume = pcie_port_device_resume,
  57. .freeze = pcie_port_device_suspend,
  58. .thaw = pcie_port_device_resume,
  59. .poweroff = pcie_port_device_suspend,
  60. .restore_noirq = pcie_port_device_resume_noirq,
  61. .restore = pcie_port_device_resume,
  62. .runtime_suspend = pcie_port_runtime_suspend,
  63. .runtime_resume = pcie_port_device_runtime_resume,
  64. .runtime_idle = pcie_port_runtime_idle,
  65. };
  66. #define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
  67. #else /* !PM */
  68. #define PCIE_PORTDRV_PM_OPS NULL
  69. #endif /* !PM */
  70. /*
  71. * pcie_portdrv_probe - Probe PCI-Express port devices
  72. * @dev: PCI-Express port device being probed
  73. *
  74. * If detected invokes the pcie_port_device_register() method for
  75. * this port device.
  76. *
  77. */
  78. static int pcie_portdrv_probe(struct pci_dev *dev,
  79. const struct pci_device_id *id)
  80. {
  81. int status;
  82. if (!pci_is_pcie(dev) ||
  83. ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
  84. (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) &&
  85. (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
  86. return -ENODEV;
  87. status = pcie_port_device_register(dev);
  88. if (status)
  89. return status;
  90. pci_save_state(dev);
  91. dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NEVER_SKIP |
  92. DPM_FLAG_SMART_SUSPEND);
  93. if (pci_bridge_d3_possible(dev)) {
  94. /*
  95. * Keep the port resumed 100ms to make sure things like
  96. * config space accesses from userspace (lspci) will not
  97. * cause the port to repeatedly suspend and resume.
  98. */
  99. pm_runtime_set_autosuspend_delay(&dev->dev, 100);
  100. pm_runtime_use_autosuspend(&dev->dev);
  101. pm_runtime_mark_last_busy(&dev->dev);
  102. pm_runtime_put_autosuspend(&dev->dev);
  103. pm_runtime_allow(&dev->dev);
  104. }
  105. return 0;
  106. }
  107. static void pcie_portdrv_remove(struct pci_dev *dev)
  108. {
  109. if (pci_bridge_d3_possible(dev)) {
  110. pm_runtime_forbid(&dev->dev);
  111. pm_runtime_get_noresume(&dev->dev);
  112. pm_runtime_dont_use_autosuspend(&dev->dev);
  113. }
  114. pcie_port_device_remove(dev);
  115. }
  116. static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
  117. enum pci_channel_state error)
  118. {
  119. /* Root Port has no impact. Always recovers. */
  120. return PCI_ERS_RESULT_CAN_RECOVER;
  121. }
  122. static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev)
  123. {
  124. pci_restore_state(dev);
  125. pci_save_state(dev);
  126. return PCI_ERS_RESULT_RECOVERED;
  127. }
  128. static pci_ers_result_t pcie_portdrv_mmio_enabled(struct pci_dev *dev)
  129. {
  130. return PCI_ERS_RESULT_RECOVERED;
  131. }
  132. static int resume_iter(struct device *device, void *data)
  133. {
  134. struct pcie_device *pcie_device;
  135. struct pcie_port_service_driver *driver;
  136. if (device->bus == &pcie_port_bus_type && device->driver) {
  137. driver = to_service_driver(device->driver);
  138. if (driver && driver->error_resume) {
  139. pcie_device = to_pcie_device(device);
  140. /* Forward error message to service drivers */
  141. driver->error_resume(pcie_device->port);
  142. }
  143. }
  144. return 0;
  145. }
  146. static void pcie_portdrv_err_resume(struct pci_dev *dev)
  147. {
  148. device_for_each_child(&dev->dev, NULL, resume_iter);
  149. }
  150. /*
  151. * LINUX Device Driver Model
  152. */
  153. static const struct pci_device_id port_pci_ids[] = { {
  154. /* handle any PCI-Express port */
  155. PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0),
  156. }, { /* end: all zeroes */ }
  157. };
  158. static const struct pci_error_handlers pcie_portdrv_err_handler = {
  159. .error_detected = pcie_portdrv_error_detected,
  160. .slot_reset = pcie_portdrv_slot_reset,
  161. .mmio_enabled = pcie_portdrv_mmio_enabled,
  162. .resume = pcie_portdrv_err_resume,
  163. };
  164. static struct pci_driver pcie_portdriver = {
  165. .name = "pcieport",
  166. .id_table = &port_pci_ids[0],
  167. .probe = pcie_portdrv_probe,
  168. .remove = pcie_portdrv_remove,
  169. .shutdown = pcie_portdrv_remove,
  170. .err_handler = &pcie_portdrv_err_handler,
  171. .driver.pm = PCIE_PORTDRV_PM_OPS,
  172. };
  173. static int __init dmi_pcie_pme_disable_msi(const struct dmi_system_id *d)
  174. {
  175. pr_notice("%s detected: will not use MSI for PCIe PME signaling\n",
  176. d->ident);
  177. pcie_pme_disable_msi();
  178. return 0;
  179. }
  180. static const struct dmi_system_id pcie_portdrv_dmi_table[] __initconst = {
  181. /*
  182. * Boxes that should not use MSI for PCIe PME signaling.
  183. */
  184. {
  185. .callback = dmi_pcie_pme_disable_msi,
  186. .ident = "MSI Wind U-100",
  187. .matches = {
  188. DMI_MATCH(DMI_SYS_VENDOR,
  189. "MICRO-STAR INTERNATIONAL CO., LTD"),
  190. DMI_MATCH(DMI_PRODUCT_NAME, "U-100"),
  191. },
  192. },
  193. {}
  194. };
  195. static void __init pcie_init_services(void)
  196. {
  197. pcie_aer_init();
  198. pcie_pme_init();
  199. pcie_dpc_init();
  200. pcie_hp_init();
  201. }
  202. static int __init pcie_portdrv_init(void)
  203. {
  204. if (pcie_ports_disabled)
  205. return -EACCES;
  206. pcie_init_services();
  207. dmi_check_system(pcie_portdrv_dmi_table);
  208. return pci_register_driver(&pcie_portdriver);
  209. }
  210. device_initcall(pcie_portdrv_init);