tifm_sd.c 28 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092
  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Special thanks to Brad Campbell for extensive testing of this driver.
  11. *
  12. */
  13. #include <linux/tifm.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/highmem.h>
  16. #include <linux/scatterlist.h>
  17. #include <linux/module.h>
  18. #include <asm/io.h>
  19. #define DRIVER_NAME "tifm_sd"
  20. #define DRIVER_VERSION "0.8"
  21. static bool no_dma = 0;
  22. static bool fixed_timeout = 0;
  23. module_param(no_dma, bool, 0644);
  24. module_param(fixed_timeout, bool, 0644);
  25. /* Constants here are mostly from OMAP5912 datasheet */
  26. #define TIFM_MMCSD_RESET 0x0002
  27. #define TIFM_MMCSD_CLKMASK 0x03ff
  28. #define TIFM_MMCSD_POWER 0x0800
  29. #define TIFM_MMCSD_4BBUS 0x8000
  30. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  31. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  32. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  33. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  34. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  35. #define TIFM_MMCSD_READ 0x8000
  36. #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
  37. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  38. #define TIFM_MMCSD_CD 0x0002 /* card detect */
  39. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  40. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  41. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  42. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  43. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  44. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  45. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  46. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  47. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  48. #define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
  49. #define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
  50. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  51. #define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
  52. #define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
  53. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  54. #define TIFM_MMCSD_RSP_R0 0x0000
  55. #define TIFM_MMCSD_RSP_R1 0x0100
  56. #define TIFM_MMCSD_RSP_R2 0x0200
  57. #define TIFM_MMCSD_RSP_R3 0x0300
  58. #define TIFM_MMCSD_RSP_R4 0x0400
  59. #define TIFM_MMCSD_RSP_R5 0x0500
  60. #define TIFM_MMCSD_RSP_R6 0x0600
  61. #define TIFM_MMCSD_RSP_BUSY 0x0800
  62. #define TIFM_MMCSD_CMD_BC 0x0000
  63. #define TIFM_MMCSD_CMD_BCR 0x1000
  64. #define TIFM_MMCSD_CMD_AC 0x2000
  65. #define TIFM_MMCSD_CMD_ADTC 0x3000
  66. #define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
  67. enum {
  68. CMD_READY = 0x0001,
  69. FIFO_READY = 0x0002,
  70. BRS_READY = 0x0004,
  71. SCMD_ACTIVE = 0x0008,
  72. SCMD_READY = 0x0010,
  73. CARD_BUSY = 0x0020,
  74. DATA_CARRY = 0x0040
  75. };
  76. struct tifm_sd {
  77. struct tifm_dev *dev;
  78. unsigned short eject:1,
  79. open_drain:1,
  80. no_dma:1;
  81. unsigned short cmd_flags;
  82. unsigned int clk_freq;
  83. unsigned int clk_div;
  84. unsigned long timeout_jiffies;
  85. struct tasklet_struct finish_tasklet;
  86. struct timer_list timer;
  87. struct mmc_request *req;
  88. int sg_len;
  89. int sg_pos;
  90. unsigned int block_pos;
  91. struct scatterlist bounce_buf;
  92. unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
  93. };
  94. /* for some reason, host won't respond correctly to readw/writew */
  95. static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
  96. unsigned int off, unsigned int cnt)
  97. {
  98. struct tifm_dev *sock = host->dev;
  99. unsigned char *buf;
  100. unsigned int pos = 0, val;
  101. buf = kmap_atomic(pg) + off;
  102. if (host->cmd_flags & DATA_CARRY) {
  103. buf[pos++] = host->bounce_buf_data[0];
  104. host->cmd_flags &= ~DATA_CARRY;
  105. }
  106. while (pos < cnt) {
  107. val = readl(sock->addr + SOCK_MMCSD_DATA);
  108. buf[pos++] = val & 0xff;
  109. if (pos == cnt) {
  110. host->bounce_buf_data[0] = (val >> 8) & 0xff;
  111. host->cmd_flags |= DATA_CARRY;
  112. break;
  113. }
  114. buf[pos++] = (val >> 8) & 0xff;
  115. }
  116. kunmap_atomic(buf - off);
  117. }
  118. static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
  119. unsigned int off, unsigned int cnt)
  120. {
  121. struct tifm_dev *sock = host->dev;
  122. unsigned char *buf;
  123. unsigned int pos = 0, val;
  124. buf = kmap_atomic(pg) + off;
  125. if (host->cmd_flags & DATA_CARRY) {
  126. val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
  127. writel(val, sock->addr + SOCK_MMCSD_DATA);
  128. host->cmd_flags &= ~DATA_CARRY;
  129. }
  130. while (pos < cnt) {
  131. val = buf[pos++];
  132. if (pos == cnt) {
  133. host->bounce_buf_data[0] = val & 0xff;
  134. host->cmd_flags |= DATA_CARRY;
  135. break;
  136. }
  137. val |= (buf[pos++] << 8) & 0xff00;
  138. writel(val, sock->addr + SOCK_MMCSD_DATA);
  139. }
  140. kunmap_atomic(buf - off);
  141. }
  142. static void tifm_sd_transfer_data(struct tifm_sd *host)
  143. {
  144. struct mmc_data *r_data = host->req->cmd->data;
  145. struct scatterlist *sg = r_data->sg;
  146. unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
  147. unsigned int p_off, p_cnt;
  148. struct page *pg;
  149. if (host->sg_pos == host->sg_len)
  150. return;
  151. while (t_size) {
  152. cnt = sg[host->sg_pos].length - host->block_pos;
  153. if (!cnt) {
  154. host->block_pos = 0;
  155. host->sg_pos++;
  156. if (host->sg_pos == host->sg_len) {
  157. if ((r_data->flags & MMC_DATA_WRITE)
  158. && (host->cmd_flags & DATA_CARRY))
  159. writel(host->bounce_buf_data[0],
  160. host->dev->addr
  161. + SOCK_MMCSD_DATA);
  162. return;
  163. }
  164. cnt = sg[host->sg_pos].length;
  165. }
  166. off = sg[host->sg_pos].offset + host->block_pos;
  167. pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
  168. p_off = offset_in_page(off);
  169. p_cnt = PAGE_SIZE - p_off;
  170. p_cnt = min(p_cnt, cnt);
  171. p_cnt = min(p_cnt, t_size);
  172. if (r_data->flags & MMC_DATA_READ)
  173. tifm_sd_read_fifo(host, pg, p_off, p_cnt);
  174. else if (r_data->flags & MMC_DATA_WRITE)
  175. tifm_sd_write_fifo(host, pg, p_off, p_cnt);
  176. t_size -= p_cnt;
  177. host->block_pos += p_cnt;
  178. }
  179. }
  180. static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
  181. struct page *src, unsigned int src_off,
  182. unsigned int count)
  183. {
  184. unsigned char *src_buf = kmap_atomic(src) + src_off;
  185. unsigned char *dst_buf = kmap_atomic(dst) + dst_off;
  186. memcpy(dst_buf, src_buf, count);
  187. kunmap_atomic(dst_buf - dst_off);
  188. kunmap_atomic(src_buf - src_off);
  189. }
  190. static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
  191. {
  192. struct scatterlist *sg = r_data->sg;
  193. unsigned int t_size = r_data->blksz;
  194. unsigned int off, cnt;
  195. unsigned int p_off, p_cnt;
  196. struct page *pg;
  197. dev_dbg(&host->dev->dev, "bouncing block\n");
  198. while (t_size) {
  199. cnt = sg[host->sg_pos].length - host->block_pos;
  200. if (!cnt) {
  201. host->block_pos = 0;
  202. host->sg_pos++;
  203. if (host->sg_pos == host->sg_len)
  204. return;
  205. cnt = sg[host->sg_pos].length;
  206. }
  207. off = sg[host->sg_pos].offset + host->block_pos;
  208. pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
  209. p_off = offset_in_page(off);
  210. p_cnt = PAGE_SIZE - p_off;
  211. p_cnt = min(p_cnt, cnt);
  212. p_cnt = min(p_cnt, t_size);
  213. if (r_data->flags & MMC_DATA_WRITE)
  214. tifm_sd_copy_page(sg_page(&host->bounce_buf),
  215. r_data->blksz - t_size,
  216. pg, p_off, p_cnt);
  217. else if (r_data->flags & MMC_DATA_READ)
  218. tifm_sd_copy_page(pg, p_off, sg_page(&host->bounce_buf),
  219. r_data->blksz - t_size, p_cnt);
  220. t_size -= p_cnt;
  221. host->block_pos += p_cnt;
  222. }
  223. }
  224. static int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
  225. {
  226. struct tifm_dev *sock = host->dev;
  227. unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
  228. unsigned int dma_len, dma_blk_cnt, dma_off;
  229. struct scatterlist *sg = NULL;
  230. unsigned long flags;
  231. if (host->sg_pos == host->sg_len)
  232. return 1;
  233. if (host->cmd_flags & DATA_CARRY) {
  234. host->cmd_flags &= ~DATA_CARRY;
  235. local_irq_save(flags);
  236. tifm_sd_bounce_block(host, r_data);
  237. local_irq_restore(flags);
  238. if (host->sg_pos == host->sg_len)
  239. return 1;
  240. }
  241. dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
  242. if (!dma_len) {
  243. host->block_pos = 0;
  244. host->sg_pos++;
  245. if (host->sg_pos == host->sg_len)
  246. return 1;
  247. dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
  248. }
  249. if (dma_len < t_size) {
  250. dma_blk_cnt = dma_len / r_data->blksz;
  251. dma_off = host->block_pos;
  252. host->block_pos += dma_blk_cnt * r_data->blksz;
  253. } else {
  254. dma_blk_cnt = TIFM_DMA_TSIZE;
  255. dma_off = host->block_pos;
  256. host->block_pos += t_size;
  257. }
  258. if (dma_blk_cnt)
  259. sg = &r_data->sg[host->sg_pos];
  260. else if (dma_len) {
  261. if (r_data->flags & MMC_DATA_WRITE) {
  262. local_irq_save(flags);
  263. tifm_sd_bounce_block(host, r_data);
  264. local_irq_restore(flags);
  265. } else
  266. host->cmd_flags |= DATA_CARRY;
  267. sg = &host->bounce_buf;
  268. dma_off = 0;
  269. dma_blk_cnt = 1;
  270. } else
  271. return 1;
  272. dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
  273. writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
  274. if (r_data->flags & MMC_DATA_WRITE)
  275. writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
  276. sock->addr + SOCK_DMA_CONTROL);
  277. else
  278. writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
  279. sock->addr + SOCK_DMA_CONTROL);
  280. return 0;
  281. }
  282. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  283. {
  284. unsigned int rc = 0;
  285. switch (mmc_resp_type(cmd)) {
  286. case MMC_RSP_NONE:
  287. rc |= TIFM_MMCSD_RSP_R0;
  288. break;
  289. case MMC_RSP_R1B:
  290. rc |= TIFM_MMCSD_RSP_BUSY;
  291. /* fall-through */
  292. case MMC_RSP_R1:
  293. rc |= TIFM_MMCSD_RSP_R1;
  294. break;
  295. case MMC_RSP_R2:
  296. rc |= TIFM_MMCSD_RSP_R2;
  297. break;
  298. case MMC_RSP_R3:
  299. rc |= TIFM_MMCSD_RSP_R3;
  300. break;
  301. default:
  302. BUG();
  303. }
  304. switch (mmc_cmd_type(cmd)) {
  305. case MMC_CMD_BC:
  306. rc |= TIFM_MMCSD_CMD_BC;
  307. break;
  308. case MMC_CMD_BCR:
  309. rc |= TIFM_MMCSD_CMD_BCR;
  310. break;
  311. case MMC_CMD_AC:
  312. rc |= TIFM_MMCSD_CMD_AC;
  313. break;
  314. case MMC_CMD_ADTC:
  315. rc |= TIFM_MMCSD_CMD_ADTC;
  316. break;
  317. default:
  318. BUG();
  319. }
  320. return rc;
  321. }
  322. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  323. {
  324. struct tifm_dev *sock = host->dev;
  325. unsigned int cmd_mask = tifm_sd_op_flags(cmd);
  326. if (host->open_drain)
  327. cmd_mask |= TIFM_MMCSD_ODTO;
  328. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  329. cmd_mask |= TIFM_MMCSD_READ;
  330. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  331. cmd->opcode, cmd->arg, cmd_mask);
  332. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  333. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  334. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  335. }
  336. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  337. {
  338. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  339. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  340. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  341. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  342. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  343. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  344. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  345. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  346. }
  347. static void tifm_sd_check_status(struct tifm_sd *host)
  348. {
  349. struct tifm_dev *sock = host->dev;
  350. struct mmc_command *cmd = host->req->cmd;
  351. if (cmd->error)
  352. goto finish_request;
  353. if (!(host->cmd_flags & CMD_READY))
  354. return;
  355. if (cmd->data) {
  356. if (cmd->data->error) {
  357. if ((host->cmd_flags & SCMD_ACTIVE)
  358. && !(host->cmd_flags & SCMD_READY))
  359. return;
  360. goto finish_request;
  361. }
  362. if (!(host->cmd_flags & BRS_READY))
  363. return;
  364. if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
  365. return;
  366. if (cmd->data->flags & MMC_DATA_WRITE) {
  367. if (host->req->stop) {
  368. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  369. host->cmd_flags |= SCMD_ACTIVE;
  370. writel(TIFM_MMCSD_EOFB
  371. | readl(sock->addr
  372. + SOCK_MMCSD_INT_ENABLE),
  373. sock->addr
  374. + SOCK_MMCSD_INT_ENABLE);
  375. tifm_sd_exec(host, host->req->stop);
  376. return;
  377. } else {
  378. if (!(host->cmd_flags & SCMD_READY)
  379. || (host->cmd_flags & CARD_BUSY))
  380. return;
  381. writel((~TIFM_MMCSD_EOFB)
  382. & readl(sock->addr
  383. + SOCK_MMCSD_INT_ENABLE),
  384. sock->addr
  385. + SOCK_MMCSD_INT_ENABLE);
  386. }
  387. } else {
  388. if (host->cmd_flags & CARD_BUSY)
  389. return;
  390. writel((~TIFM_MMCSD_EOFB)
  391. & readl(sock->addr
  392. + SOCK_MMCSD_INT_ENABLE),
  393. sock->addr + SOCK_MMCSD_INT_ENABLE);
  394. }
  395. } else {
  396. if (host->req->stop) {
  397. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  398. host->cmd_flags |= SCMD_ACTIVE;
  399. tifm_sd_exec(host, host->req->stop);
  400. return;
  401. } else {
  402. if (!(host->cmd_flags & SCMD_READY))
  403. return;
  404. }
  405. }
  406. }
  407. }
  408. finish_request:
  409. tasklet_schedule(&host->finish_tasklet);
  410. }
  411. /* Called from interrupt handler */
  412. static void tifm_sd_data_event(struct tifm_dev *sock)
  413. {
  414. struct tifm_sd *host;
  415. unsigned int fifo_status = 0;
  416. struct mmc_data *r_data = NULL;
  417. spin_lock(&sock->lock);
  418. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  419. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  420. dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
  421. fifo_status, host->cmd_flags);
  422. if (host->req) {
  423. r_data = host->req->cmd->data;
  424. if (r_data && (fifo_status & TIFM_FIFO_READY)) {
  425. if (tifm_sd_set_dma_data(host, r_data)) {
  426. host->cmd_flags |= FIFO_READY;
  427. tifm_sd_check_status(host);
  428. }
  429. }
  430. }
  431. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  432. spin_unlock(&sock->lock);
  433. }
  434. /* Called from interrupt handler */
  435. static void tifm_sd_card_event(struct tifm_dev *sock)
  436. {
  437. struct tifm_sd *host;
  438. unsigned int host_status = 0;
  439. int cmd_error = 0;
  440. struct mmc_command *cmd = NULL;
  441. unsigned long flags;
  442. spin_lock(&sock->lock);
  443. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  444. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  445. dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
  446. host_status, host->cmd_flags);
  447. if (host->req) {
  448. cmd = host->req->cmd;
  449. if (host_status & TIFM_MMCSD_ERRMASK) {
  450. writel(host_status & TIFM_MMCSD_ERRMASK,
  451. sock->addr + SOCK_MMCSD_STATUS);
  452. if (host_status & TIFM_MMCSD_CTO)
  453. cmd_error = -ETIMEDOUT;
  454. else if (host_status & TIFM_MMCSD_CCRC)
  455. cmd_error = -EILSEQ;
  456. if (cmd->data) {
  457. if (host_status & TIFM_MMCSD_DTO)
  458. cmd->data->error = -ETIMEDOUT;
  459. else if (host_status & TIFM_MMCSD_DCRC)
  460. cmd->data->error = -EILSEQ;
  461. }
  462. writel(TIFM_FIFO_INT_SETALL,
  463. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  464. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  465. if (host->req->stop) {
  466. if (host->cmd_flags & SCMD_ACTIVE) {
  467. host->req->stop->error = cmd_error;
  468. host->cmd_flags |= SCMD_READY;
  469. } else {
  470. cmd->error = cmd_error;
  471. host->cmd_flags |= SCMD_ACTIVE;
  472. tifm_sd_exec(host, host->req->stop);
  473. goto done;
  474. }
  475. } else
  476. cmd->error = cmd_error;
  477. } else {
  478. if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
  479. if (!(host->cmd_flags & CMD_READY)) {
  480. host->cmd_flags |= CMD_READY;
  481. tifm_sd_fetch_resp(cmd, sock);
  482. } else if (host->cmd_flags & SCMD_ACTIVE) {
  483. host->cmd_flags |= SCMD_READY;
  484. tifm_sd_fetch_resp(host->req->stop,
  485. sock);
  486. }
  487. }
  488. if (host_status & TIFM_MMCSD_BRS)
  489. host->cmd_flags |= BRS_READY;
  490. }
  491. if (host->no_dma && cmd->data) {
  492. if (host_status & TIFM_MMCSD_AE)
  493. writel(host_status & TIFM_MMCSD_AE,
  494. sock->addr + SOCK_MMCSD_STATUS);
  495. if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
  496. | TIFM_MMCSD_BRS)) {
  497. local_irq_save(flags);
  498. tifm_sd_transfer_data(host);
  499. local_irq_restore(flags);
  500. host_status &= ~TIFM_MMCSD_AE;
  501. }
  502. }
  503. if (host_status & TIFM_MMCSD_EOFB)
  504. host->cmd_flags &= ~CARD_BUSY;
  505. else if (host_status & TIFM_MMCSD_CB)
  506. host->cmd_flags |= CARD_BUSY;
  507. tifm_sd_check_status(host);
  508. }
  509. done:
  510. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  511. spin_unlock(&sock->lock);
  512. }
  513. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  514. struct mmc_data *data)
  515. {
  516. struct tifm_dev *sock = host->dev;
  517. unsigned int data_timeout = data->timeout_clks;
  518. if (fixed_timeout)
  519. return;
  520. data_timeout += data->timeout_ns /
  521. ((1000000000UL / host->clk_freq) * host->clk_div);
  522. if (data_timeout < 0xffff) {
  523. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  524. writel((~TIFM_MMCSD_DPE)
  525. & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  526. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  527. } else {
  528. data_timeout = (data_timeout >> 10) + 1;
  529. if (data_timeout > 0xffff)
  530. data_timeout = 0; /* set to unlimited */
  531. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  532. writel(TIFM_MMCSD_DPE
  533. | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  534. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  535. }
  536. }
  537. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  538. {
  539. struct tifm_sd *host = mmc_priv(mmc);
  540. struct tifm_dev *sock = host->dev;
  541. unsigned long flags;
  542. struct mmc_data *r_data = mrq->cmd->data;
  543. spin_lock_irqsave(&sock->lock, flags);
  544. if (host->eject) {
  545. mrq->cmd->error = -ENOMEDIUM;
  546. goto err_out;
  547. }
  548. if (host->req) {
  549. pr_err("%s : unfinished request detected\n",
  550. dev_name(&sock->dev));
  551. mrq->cmd->error = -ETIMEDOUT;
  552. goto err_out;
  553. }
  554. host->cmd_flags = 0;
  555. host->block_pos = 0;
  556. host->sg_pos = 0;
  557. if (mrq->data && !is_power_of_2(mrq->data->blksz))
  558. host->no_dma = 1;
  559. else
  560. host->no_dma = no_dma ? 1 : 0;
  561. if (r_data) {
  562. tifm_sd_set_data_timeout(host, r_data);
  563. if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
  564. writel(TIFM_MMCSD_EOFB
  565. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  566. sock->addr + SOCK_MMCSD_INT_ENABLE);
  567. if (host->no_dma) {
  568. writel(TIFM_MMCSD_BUFINT
  569. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  570. sock->addr + SOCK_MMCSD_INT_ENABLE);
  571. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
  572. | (TIFM_MMCSD_FIFO_SIZE - 1),
  573. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  574. host->sg_len = r_data->sg_len;
  575. } else {
  576. sg_init_one(&host->bounce_buf, host->bounce_buf_data,
  577. r_data->blksz);
  578. if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
  579. r_data->flags & MMC_DATA_WRITE
  580. ? PCI_DMA_TODEVICE
  581. : PCI_DMA_FROMDEVICE)) {
  582. pr_err("%s : scatterlist map failed\n",
  583. dev_name(&sock->dev));
  584. mrq->cmd->error = -ENOMEM;
  585. goto err_out;
  586. }
  587. host->sg_len = tifm_map_sg(sock, r_data->sg,
  588. r_data->sg_len,
  589. r_data->flags
  590. & MMC_DATA_WRITE
  591. ? PCI_DMA_TODEVICE
  592. : PCI_DMA_FROMDEVICE);
  593. if (host->sg_len < 1) {
  594. pr_err("%s : scatterlist map failed\n",
  595. dev_name(&sock->dev));
  596. tifm_unmap_sg(sock, &host->bounce_buf, 1,
  597. r_data->flags & MMC_DATA_WRITE
  598. ? PCI_DMA_TODEVICE
  599. : PCI_DMA_FROMDEVICE);
  600. mrq->cmd->error = -ENOMEM;
  601. goto err_out;
  602. }
  603. writel(TIFM_FIFO_INT_SETALL,
  604. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  605. writel(ilog2(r_data->blksz) - 2,
  606. sock->addr + SOCK_FIFO_PAGE_SIZE);
  607. writel(TIFM_FIFO_ENABLE,
  608. sock->addr + SOCK_FIFO_CONTROL);
  609. writel(TIFM_FIFO_INTMASK,
  610. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  611. if (r_data->flags & MMC_DATA_WRITE)
  612. writel(TIFM_MMCSD_TXDE,
  613. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  614. else
  615. writel(TIFM_MMCSD_RXDE,
  616. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  617. tifm_sd_set_dma_data(host, r_data);
  618. }
  619. writel(r_data->blocks - 1,
  620. sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  621. writel(r_data->blksz - 1,
  622. sock->addr + SOCK_MMCSD_BLOCK_LEN);
  623. }
  624. host->req = mrq;
  625. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  626. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  627. sock->addr + SOCK_CONTROL);
  628. tifm_sd_exec(host, mrq->cmd);
  629. spin_unlock_irqrestore(&sock->lock, flags);
  630. return;
  631. err_out:
  632. spin_unlock_irqrestore(&sock->lock, flags);
  633. mmc_request_done(mmc, mrq);
  634. }
  635. static void tifm_sd_end_cmd(unsigned long data)
  636. {
  637. struct tifm_sd *host = (struct tifm_sd*)data;
  638. struct tifm_dev *sock = host->dev;
  639. struct mmc_host *mmc = tifm_get_drvdata(sock);
  640. struct mmc_request *mrq;
  641. struct mmc_data *r_data = NULL;
  642. unsigned long flags;
  643. spin_lock_irqsave(&sock->lock, flags);
  644. del_timer(&host->timer);
  645. mrq = host->req;
  646. host->req = NULL;
  647. if (!mrq) {
  648. pr_err(" %s : no request to complete?\n",
  649. dev_name(&sock->dev));
  650. spin_unlock_irqrestore(&sock->lock, flags);
  651. return;
  652. }
  653. r_data = mrq->cmd->data;
  654. if (r_data) {
  655. if (host->no_dma) {
  656. writel((~TIFM_MMCSD_BUFINT)
  657. & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  658. sock->addr + SOCK_MMCSD_INT_ENABLE);
  659. } else {
  660. tifm_unmap_sg(sock, &host->bounce_buf, 1,
  661. (r_data->flags & MMC_DATA_WRITE)
  662. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  663. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  664. (r_data->flags & MMC_DATA_WRITE)
  665. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  666. }
  667. r_data->bytes_xfered = r_data->blocks
  668. - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  669. r_data->bytes_xfered *= r_data->blksz;
  670. r_data->bytes_xfered += r_data->blksz
  671. - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  672. }
  673. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  674. sock->addr + SOCK_CONTROL);
  675. spin_unlock_irqrestore(&sock->lock, flags);
  676. mmc_request_done(mmc, mrq);
  677. }
  678. static void tifm_sd_abort(struct timer_list *t)
  679. {
  680. struct tifm_sd *host = from_timer(host, t, timer);
  681. pr_err("%s : card failed to respond for a long period of time "
  682. "(%x, %x)\n",
  683. dev_name(&host->dev->dev), host->req->cmd->opcode, host->cmd_flags);
  684. tifm_eject(host->dev);
  685. }
  686. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  687. {
  688. struct tifm_sd *host = mmc_priv(mmc);
  689. struct tifm_dev *sock = host->dev;
  690. unsigned int clk_div1, clk_div2;
  691. unsigned long flags;
  692. spin_lock_irqsave(&sock->lock, flags);
  693. dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
  694. "chip_select = %x, power_mode = %x, bus_width = %x\n",
  695. ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
  696. ios->power_mode, ios->bus_width);
  697. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  698. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  699. sock->addr + SOCK_MMCSD_CONFIG);
  700. } else {
  701. writel((~TIFM_MMCSD_4BBUS)
  702. & readl(sock->addr + SOCK_MMCSD_CONFIG),
  703. sock->addr + SOCK_MMCSD_CONFIG);
  704. }
  705. if (ios->clock) {
  706. clk_div1 = 20000000 / ios->clock;
  707. if (!clk_div1)
  708. clk_div1 = 1;
  709. clk_div2 = 24000000 / ios->clock;
  710. if (!clk_div2)
  711. clk_div2 = 1;
  712. if ((20000000 / clk_div1) > ios->clock)
  713. clk_div1++;
  714. if ((24000000 / clk_div2) > ios->clock)
  715. clk_div2++;
  716. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  717. host->clk_freq = 20000000;
  718. host->clk_div = clk_div1;
  719. writel((~TIFM_CTRL_FAST_CLK)
  720. & readl(sock->addr + SOCK_CONTROL),
  721. sock->addr + SOCK_CONTROL);
  722. } else {
  723. host->clk_freq = 24000000;
  724. host->clk_div = clk_div2;
  725. writel(TIFM_CTRL_FAST_CLK
  726. | readl(sock->addr + SOCK_CONTROL),
  727. sock->addr + SOCK_CONTROL);
  728. }
  729. } else {
  730. host->clk_div = 0;
  731. }
  732. host->clk_div &= TIFM_MMCSD_CLKMASK;
  733. writel(host->clk_div
  734. | ((~TIFM_MMCSD_CLKMASK)
  735. & readl(sock->addr + SOCK_MMCSD_CONFIG)),
  736. sock->addr + SOCK_MMCSD_CONFIG);
  737. host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
  738. /* chip_select : maybe later */
  739. //vdd
  740. //power is set before probe / after remove
  741. spin_unlock_irqrestore(&sock->lock, flags);
  742. }
  743. static int tifm_sd_ro(struct mmc_host *mmc)
  744. {
  745. int rc = 0;
  746. struct tifm_sd *host = mmc_priv(mmc);
  747. struct tifm_dev *sock = host->dev;
  748. unsigned long flags;
  749. spin_lock_irqsave(&sock->lock, flags);
  750. if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
  751. rc = 1;
  752. spin_unlock_irqrestore(&sock->lock, flags);
  753. return rc;
  754. }
  755. static const struct mmc_host_ops tifm_sd_ops = {
  756. .request = tifm_sd_request,
  757. .set_ios = tifm_sd_ios,
  758. .get_ro = tifm_sd_ro
  759. };
  760. static int tifm_sd_initialize_host(struct tifm_sd *host)
  761. {
  762. int rc;
  763. unsigned int host_status = 0;
  764. struct tifm_dev *sock = host->dev;
  765. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  766. mmiowb();
  767. host->clk_div = 61;
  768. host->clk_freq = 20000000;
  769. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  770. writel(host->clk_div | TIFM_MMCSD_POWER,
  771. sock->addr + SOCK_MMCSD_CONFIG);
  772. /* wait up to 0.51 sec for reset */
  773. for (rc = 32; rc <= 256; rc <<= 1) {
  774. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  775. rc = 0;
  776. break;
  777. }
  778. msleep(rc);
  779. }
  780. if (rc) {
  781. pr_err("%s : controller failed to reset\n",
  782. dev_name(&sock->dev));
  783. return -ENODEV;
  784. }
  785. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  786. writel(host->clk_div | TIFM_MMCSD_POWER,
  787. sock->addr + SOCK_MMCSD_CONFIG);
  788. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  789. // command timeout fixed to 64 clocks for now
  790. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
  791. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  792. for (rc = 16; rc <= 64; rc <<= 1) {
  793. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  794. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  795. if (!(host_status & TIFM_MMCSD_ERRMASK)
  796. && (host_status & TIFM_MMCSD_EOC)) {
  797. rc = 0;
  798. break;
  799. }
  800. msleep(rc);
  801. }
  802. if (rc) {
  803. pr_err("%s : card not ready - probe failed on initialization\n",
  804. dev_name(&sock->dev));
  805. return -ENODEV;
  806. }
  807. writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
  808. | TIFM_MMCSD_ERRMASK,
  809. sock->addr + SOCK_MMCSD_INT_ENABLE);
  810. mmiowb();
  811. return 0;
  812. }
  813. static int tifm_sd_probe(struct tifm_dev *sock)
  814. {
  815. struct mmc_host *mmc;
  816. struct tifm_sd *host;
  817. int rc = -EIO;
  818. if (!(TIFM_SOCK_STATE_OCCUPIED
  819. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  820. pr_warn("%s : card gone, unexpectedly\n",
  821. dev_name(&sock->dev));
  822. return rc;
  823. }
  824. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  825. if (!mmc)
  826. return -ENOMEM;
  827. host = mmc_priv(mmc);
  828. tifm_set_drvdata(sock, mmc);
  829. host->dev = sock;
  830. host->timeout_jiffies = msecs_to_jiffies(1000);
  831. tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
  832. (unsigned long)host);
  833. timer_setup(&host->timer, tifm_sd_abort, 0);
  834. mmc->ops = &tifm_sd_ops;
  835. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  836. mmc->caps = MMC_CAP_4_BIT_DATA;
  837. mmc->f_min = 20000000 / 60;
  838. mmc->f_max = 24000000;
  839. mmc->max_blk_count = 2048;
  840. mmc->max_segs = mmc->max_blk_count;
  841. mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
  842. mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
  843. mmc->max_req_size = mmc->max_seg_size;
  844. sock->card_event = tifm_sd_card_event;
  845. sock->data_event = tifm_sd_data_event;
  846. rc = tifm_sd_initialize_host(host);
  847. if (!rc)
  848. rc = mmc_add_host(mmc);
  849. if (!rc)
  850. return 0;
  851. mmc_free_host(mmc);
  852. return rc;
  853. }
  854. static void tifm_sd_remove(struct tifm_dev *sock)
  855. {
  856. struct mmc_host *mmc = tifm_get_drvdata(sock);
  857. struct tifm_sd *host = mmc_priv(mmc);
  858. unsigned long flags;
  859. spin_lock_irqsave(&sock->lock, flags);
  860. host->eject = 1;
  861. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  862. mmiowb();
  863. spin_unlock_irqrestore(&sock->lock, flags);
  864. tasklet_kill(&host->finish_tasklet);
  865. spin_lock_irqsave(&sock->lock, flags);
  866. if (host->req) {
  867. writel(TIFM_FIFO_INT_SETALL,
  868. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  869. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  870. host->req->cmd->error = -ENOMEDIUM;
  871. if (host->req->stop)
  872. host->req->stop->error = -ENOMEDIUM;
  873. tasklet_schedule(&host->finish_tasklet);
  874. }
  875. spin_unlock_irqrestore(&sock->lock, flags);
  876. mmc_remove_host(mmc);
  877. dev_dbg(&sock->dev, "after remove\n");
  878. mmc_free_host(mmc);
  879. }
  880. #ifdef CONFIG_PM
  881. static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
  882. {
  883. return 0;
  884. }
  885. static int tifm_sd_resume(struct tifm_dev *sock)
  886. {
  887. struct mmc_host *mmc = tifm_get_drvdata(sock);
  888. struct tifm_sd *host = mmc_priv(mmc);
  889. int rc;
  890. rc = tifm_sd_initialize_host(host);
  891. dev_dbg(&sock->dev, "resume initialize %d\n", rc);
  892. if (rc)
  893. host->eject = 1;
  894. return rc;
  895. }
  896. #else
  897. #define tifm_sd_suspend NULL
  898. #define tifm_sd_resume NULL
  899. #endif /* CONFIG_PM */
  900. static struct tifm_device_id tifm_sd_id_tbl[] = {
  901. { TIFM_TYPE_SD }, { }
  902. };
  903. static struct tifm_driver tifm_sd_driver = {
  904. .driver = {
  905. .name = DRIVER_NAME,
  906. .owner = THIS_MODULE
  907. },
  908. .id_table = tifm_sd_id_tbl,
  909. .probe = tifm_sd_probe,
  910. .remove = tifm_sd_remove,
  911. .suspend = tifm_sd_suspend,
  912. .resume = tifm_sd_resume
  913. };
  914. static int __init tifm_sd_init(void)
  915. {
  916. return tifm_register_driver(&tifm_sd_driver);
  917. }
  918. static void __exit tifm_sd_exit(void)
  919. {
  920. tifm_unregister_driver(&tifm_sd_driver);
  921. }
  922. MODULE_AUTHOR("Alex Dubov");
  923. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  924. MODULE_LICENSE("GPL");
  925. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  926. MODULE_VERSION(DRIVER_VERSION);
  927. module_init(tifm_sd_init);
  928. module_exit(tifm_sd_exit);