renesas_sdhi_sys_dmac.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * DMA support use of SYS DMAC with SDHI SD/SDIO controller
  4. *
  5. * Copyright (C) 2016-17 Renesas Electronics Corporation
  6. * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
  7. * Copyright (C) 2017 Horms Solutions, Simon Horman
  8. * Copyright (C) 2010-2011 Guennadi Liakhovetski
  9. */
  10. #include <linux/device.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/mfd/tmio.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/module.h>
  17. #include <linux/of_device.h>
  18. #include <linux/pagemap.h>
  19. #include <linux/scatterlist.h>
  20. #include <linux/sys_soc.h>
  21. #include "renesas_sdhi.h"
  22. #include "tmio_mmc.h"
  23. #define TMIO_MMC_MIN_DMA_LEN 8
  24. static const struct renesas_sdhi_of_data of_default_cfg = {
  25. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
  26. };
  27. static const struct renesas_sdhi_of_data of_rz_compatible = {
  28. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT |
  29. TMIO_MMC_HAVE_CBSY,
  30. .tmio_ocr_mask = MMC_VDD_32_33,
  31. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  32. };
  33. static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
  34. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
  35. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  36. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  37. };
  38. /* Definitions for sampling clocks */
  39. static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = {
  40. {
  41. .clk_rate = 156000000,
  42. .tap = 0x00000703,
  43. },
  44. {
  45. .clk_rate = 0,
  46. .tap = 0x00000300,
  47. },
  48. };
  49. static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
  50. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  51. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  52. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  53. MMC_CAP_CMD23,
  54. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  55. .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
  56. .dma_rx_offset = 0x2000,
  57. .scc_offset = 0x0300,
  58. .taps = rcar_gen2_scc_taps,
  59. .taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
  60. };
  61. /* Definitions for sampling clocks */
  62. static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
  63. {
  64. .clk_rate = 0,
  65. .tap = 0x00000300,
  66. },
  67. };
  68. static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
  69. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  70. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
  71. TMIO_MMC_HAVE_4TAP_HS400,
  72. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  73. MMC_CAP_CMD23,
  74. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  75. .bus_shift = 2,
  76. .scc_offset = 0x1000,
  77. .taps = rcar_gen3_scc_taps,
  78. .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
  79. };
  80. static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
  81. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  82. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  83. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  84. MMC_CAP_CMD23,
  85. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  86. .bus_shift = 2,
  87. .scc_offset = 0x1000,
  88. .taps = rcar_gen3_scc_taps,
  89. .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
  90. };
  91. static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
  92. { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
  93. { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
  94. { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
  95. { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
  96. { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
  97. { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
  98. { .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
  99. { .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
  100. { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
  101. { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
  102. { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
  103. { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
  104. { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
  105. { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, },
  106. { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, },
  107. { .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
  108. { .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
  109. { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
  110. { .compatible = "renesas,sdhi-shmobile" },
  111. {},
  112. };
  113. MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
  114. static void renesas_sdhi_sys_dmac_enable_dma(struct tmio_mmc_host *host,
  115. bool enable)
  116. {
  117. struct renesas_sdhi *priv = host_to_priv(host);
  118. if (!host->chan_tx || !host->chan_rx)
  119. return;
  120. if (priv->dma_priv.enable)
  121. priv->dma_priv.enable(host, enable);
  122. }
  123. static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
  124. {
  125. renesas_sdhi_sys_dmac_enable_dma(host, false);
  126. if (host->chan_rx)
  127. dmaengine_terminate_all(host->chan_rx);
  128. if (host->chan_tx)
  129. dmaengine_terminate_all(host->chan_tx);
  130. renesas_sdhi_sys_dmac_enable_dma(host, true);
  131. }
  132. static void renesas_sdhi_sys_dmac_dataend_dma(struct tmio_mmc_host *host)
  133. {
  134. struct renesas_sdhi *priv = host_to_priv(host);
  135. complete(&priv->dma_priv.dma_dataend);
  136. }
  137. static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
  138. {
  139. struct tmio_mmc_host *host = arg;
  140. struct renesas_sdhi *priv = host_to_priv(host);
  141. spin_lock_irq(&host->lock);
  142. if (!host->data)
  143. goto out;
  144. if (host->data->flags & MMC_DATA_READ)
  145. dma_unmap_sg(host->chan_rx->device->dev,
  146. host->sg_ptr, host->sg_len,
  147. DMA_FROM_DEVICE);
  148. else
  149. dma_unmap_sg(host->chan_tx->device->dev,
  150. host->sg_ptr, host->sg_len,
  151. DMA_TO_DEVICE);
  152. spin_unlock_irq(&host->lock);
  153. wait_for_completion(&priv->dma_priv.dma_dataend);
  154. spin_lock_irq(&host->lock);
  155. tmio_mmc_do_data_irq(host);
  156. out:
  157. spin_unlock_irq(&host->lock);
  158. }
  159. static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
  160. {
  161. struct renesas_sdhi *priv = host_to_priv(host);
  162. struct scatterlist *sg = host->sg_ptr, *sg_tmp;
  163. struct dma_async_tx_descriptor *desc = NULL;
  164. struct dma_chan *chan = host->chan_rx;
  165. dma_cookie_t cookie;
  166. int ret, i;
  167. bool aligned = true, multiple = true;
  168. unsigned int align = (1 << host->pdata->alignment_shift) - 1;
  169. for_each_sg(sg, sg_tmp, host->sg_len, i) {
  170. if (sg_tmp->offset & align)
  171. aligned = false;
  172. if (sg_tmp->length & align) {
  173. multiple = false;
  174. break;
  175. }
  176. }
  177. if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
  178. (align & PAGE_MASK))) || !multiple) {
  179. ret = -EINVAL;
  180. goto pio;
  181. }
  182. if (sg->length < TMIO_MMC_MIN_DMA_LEN)
  183. return;
  184. /* The only sg element can be unaligned, use our bounce buffer then */
  185. if (!aligned) {
  186. sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
  187. host->sg_ptr = &host->bounce_sg;
  188. sg = host->sg_ptr;
  189. }
  190. ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
  191. if (ret > 0)
  192. desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_DEV_TO_MEM,
  193. DMA_CTRL_ACK);
  194. if (desc) {
  195. reinit_completion(&priv->dma_priv.dma_dataend);
  196. desc->callback = renesas_sdhi_sys_dmac_dma_callback;
  197. desc->callback_param = host;
  198. cookie = dmaengine_submit(desc);
  199. if (cookie < 0) {
  200. desc = NULL;
  201. ret = cookie;
  202. }
  203. host->dma_on = true;
  204. }
  205. pio:
  206. if (!desc) {
  207. /* DMA failed, fall back to PIO */
  208. renesas_sdhi_sys_dmac_enable_dma(host, false);
  209. if (ret >= 0)
  210. ret = -EIO;
  211. host->chan_rx = NULL;
  212. dma_release_channel(chan);
  213. /* Free the Tx channel too */
  214. chan = host->chan_tx;
  215. if (chan) {
  216. host->chan_tx = NULL;
  217. dma_release_channel(chan);
  218. }
  219. dev_warn(&host->pdev->dev,
  220. "DMA failed: %d, falling back to PIO\n", ret);
  221. }
  222. }
  223. static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
  224. {
  225. struct renesas_sdhi *priv = host_to_priv(host);
  226. struct scatterlist *sg = host->sg_ptr, *sg_tmp;
  227. struct dma_async_tx_descriptor *desc = NULL;
  228. struct dma_chan *chan = host->chan_tx;
  229. dma_cookie_t cookie;
  230. int ret, i;
  231. bool aligned = true, multiple = true;
  232. unsigned int align = (1 << host->pdata->alignment_shift) - 1;
  233. for_each_sg(sg, sg_tmp, host->sg_len, i) {
  234. if (sg_tmp->offset & align)
  235. aligned = false;
  236. if (sg_tmp->length & align) {
  237. multiple = false;
  238. break;
  239. }
  240. }
  241. if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
  242. (align & PAGE_MASK))) || !multiple) {
  243. ret = -EINVAL;
  244. goto pio;
  245. }
  246. if (sg->length < TMIO_MMC_MIN_DMA_LEN)
  247. return;
  248. /* The only sg element can be unaligned, use our bounce buffer then */
  249. if (!aligned) {
  250. unsigned long flags;
  251. void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
  252. sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
  253. memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
  254. tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr);
  255. host->sg_ptr = &host->bounce_sg;
  256. sg = host->sg_ptr;
  257. }
  258. ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
  259. if (ret > 0)
  260. desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_MEM_TO_DEV,
  261. DMA_CTRL_ACK);
  262. if (desc) {
  263. reinit_completion(&priv->dma_priv.dma_dataend);
  264. desc->callback = renesas_sdhi_sys_dmac_dma_callback;
  265. desc->callback_param = host;
  266. cookie = dmaengine_submit(desc);
  267. if (cookie < 0) {
  268. desc = NULL;
  269. ret = cookie;
  270. }
  271. host->dma_on = true;
  272. }
  273. pio:
  274. if (!desc) {
  275. /* DMA failed, fall back to PIO */
  276. renesas_sdhi_sys_dmac_enable_dma(host, false);
  277. if (ret >= 0)
  278. ret = -EIO;
  279. host->chan_tx = NULL;
  280. dma_release_channel(chan);
  281. /* Free the Rx channel too */
  282. chan = host->chan_rx;
  283. if (chan) {
  284. host->chan_rx = NULL;
  285. dma_release_channel(chan);
  286. }
  287. dev_warn(&host->pdev->dev,
  288. "DMA failed: %d, falling back to PIO\n", ret);
  289. }
  290. }
  291. static void renesas_sdhi_sys_dmac_start_dma(struct tmio_mmc_host *host,
  292. struct mmc_data *data)
  293. {
  294. if (data->flags & MMC_DATA_READ) {
  295. if (host->chan_rx)
  296. renesas_sdhi_sys_dmac_start_dma_rx(host);
  297. } else {
  298. if (host->chan_tx)
  299. renesas_sdhi_sys_dmac_start_dma_tx(host);
  300. }
  301. }
  302. static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
  303. {
  304. struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
  305. struct dma_chan *chan = NULL;
  306. spin_lock_irq(&host->lock);
  307. if (host->data) {
  308. if (host->data->flags & MMC_DATA_READ)
  309. chan = host->chan_rx;
  310. else
  311. chan = host->chan_tx;
  312. }
  313. spin_unlock_irq(&host->lock);
  314. tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
  315. if (chan)
  316. dma_async_issue_pending(chan);
  317. }
  318. static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
  319. struct tmio_mmc_data *pdata)
  320. {
  321. struct renesas_sdhi *priv = host_to_priv(host);
  322. /* We can only either use DMA for both Tx and Rx or not use it at all */
  323. if (!host->pdev->dev.of_node &&
  324. (!pdata->chan_priv_tx || !pdata->chan_priv_rx))
  325. return;
  326. if (!host->chan_tx && !host->chan_rx) {
  327. struct resource *res = platform_get_resource(host->pdev,
  328. IORESOURCE_MEM, 0);
  329. struct dma_slave_config cfg = {};
  330. dma_cap_mask_t mask;
  331. int ret;
  332. if (!res)
  333. return;
  334. dma_cap_zero(mask);
  335. dma_cap_set(DMA_SLAVE, mask);
  336. host->chan_tx = dma_request_slave_channel_compat(mask,
  337. priv->dma_priv.filter, pdata->chan_priv_tx,
  338. &host->pdev->dev, "tx");
  339. dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
  340. host->chan_tx);
  341. if (!host->chan_tx)
  342. return;
  343. cfg.direction = DMA_MEM_TO_DEV;
  344. cfg.dst_addr = res->start +
  345. (CTL_SD_DATA_PORT << host->bus_shift);
  346. cfg.dst_addr_width = priv->dma_priv.dma_buswidth;
  347. if (!cfg.dst_addr_width)
  348. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  349. cfg.src_addr = 0;
  350. ret = dmaengine_slave_config(host->chan_tx, &cfg);
  351. if (ret < 0)
  352. goto ecfgtx;
  353. host->chan_rx = dma_request_slave_channel_compat(mask,
  354. priv->dma_priv.filter, pdata->chan_priv_rx,
  355. &host->pdev->dev, "rx");
  356. dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
  357. host->chan_rx);
  358. if (!host->chan_rx)
  359. goto ereqrx;
  360. cfg.direction = DMA_DEV_TO_MEM;
  361. cfg.src_addr = cfg.dst_addr + host->pdata->dma_rx_offset;
  362. cfg.src_addr_width = priv->dma_priv.dma_buswidth;
  363. if (!cfg.src_addr_width)
  364. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  365. cfg.dst_addr = 0;
  366. ret = dmaengine_slave_config(host->chan_rx, &cfg);
  367. if (ret < 0)
  368. goto ecfgrx;
  369. host->bounce_buf = (u8 *)__get_free_page(GFP_KERNEL | GFP_DMA);
  370. if (!host->bounce_buf)
  371. goto ebouncebuf;
  372. init_completion(&priv->dma_priv.dma_dataend);
  373. tasklet_init(&host->dma_issue,
  374. renesas_sdhi_sys_dmac_issue_tasklet_fn,
  375. (unsigned long)host);
  376. }
  377. renesas_sdhi_sys_dmac_enable_dma(host, true);
  378. return;
  379. ebouncebuf:
  380. ecfgrx:
  381. dma_release_channel(host->chan_rx);
  382. host->chan_rx = NULL;
  383. ereqrx:
  384. ecfgtx:
  385. dma_release_channel(host->chan_tx);
  386. host->chan_tx = NULL;
  387. }
  388. static void renesas_sdhi_sys_dmac_release_dma(struct tmio_mmc_host *host)
  389. {
  390. if (host->chan_tx) {
  391. struct dma_chan *chan = host->chan_tx;
  392. host->chan_tx = NULL;
  393. dma_release_channel(chan);
  394. }
  395. if (host->chan_rx) {
  396. struct dma_chan *chan = host->chan_rx;
  397. host->chan_rx = NULL;
  398. dma_release_channel(chan);
  399. }
  400. if (host->bounce_buf) {
  401. free_pages((unsigned long)host->bounce_buf, 0);
  402. host->bounce_buf = NULL;
  403. }
  404. }
  405. static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = {
  406. .start = renesas_sdhi_sys_dmac_start_dma,
  407. .enable = renesas_sdhi_sys_dmac_enable_dma,
  408. .request = renesas_sdhi_sys_dmac_request_dma,
  409. .release = renesas_sdhi_sys_dmac_release_dma,
  410. .abort = renesas_sdhi_sys_dmac_abort_dma,
  411. .dataend = renesas_sdhi_sys_dmac_dataend_dma,
  412. };
  413. /*
  414. * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
  415. * implementation. Currently empty as all supported ES versions use
  416. * the internal DMAC.
  417. */
  418. static const struct soc_device_attribute gen3_soc_whitelist[] = {
  419. { /* sentinel */ }
  420. };
  421. static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
  422. {
  423. if ((of_device_get_match_data(&pdev->dev) == &of_rcar_gen3_compatible ||
  424. of_device_get_match_data(&pdev->dev) == &of_rcar_r8a7795_compatible) &&
  425. !soc_device_match(gen3_soc_whitelist))
  426. return -ENODEV;
  427. return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops);
  428. }
  429. static const struct dev_pm_ops renesas_sdhi_sys_dmac_dev_pm_ops = {
  430. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  431. pm_runtime_force_resume)
  432. SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
  433. tmio_mmc_host_runtime_resume,
  434. NULL)
  435. };
  436. static struct platform_driver renesas_sys_dmac_sdhi_driver = {
  437. .driver = {
  438. .name = "sh_mobile_sdhi",
  439. .pm = &renesas_sdhi_sys_dmac_dev_pm_ops,
  440. .of_match_table = renesas_sdhi_sys_dmac_of_match,
  441. },
  442. .probe = renesas_sdhi_sys_dmac_probe,
  443. .remove = renesas_sdhi_remove,
  444. };
  445. module_platform_driver(renesas_sys_dmac_sdhi_driver);
  446. MODULE_DESCRIPTION("Renesas SDHI driver");
  447. MODULE_AUTHOR("Magnus Damm");
  448. MODULE_LICENSE("GPL v2");
  449. MODULE_ALIAS("platform:sh_mobile_sdhi");