renesas_sdhi_core.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas SDHI
  4. *
  5. * Copyright (C) 2015-17 Renesas Electronics Corporation
  6. * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
  7. * Copyright (C) 2016-17 Horms Solutions, Simon Horman
  8. * Copyright (C) 2009 Magnus Damm
  9. *
  10. * Based on "Compaq ASIC3 support":
  11. *
  12. * Copyright 2001 Compaq Computer Corporation.
  13. * Copyright 2004-2005 Phil Blundell
  14. * Copyright 2007-2008 OpenedHand Ltd.
  15. *
  16. * Authors: Phil Blundell <pb@handhelds.org>,
  17. * Samuel Ortiz <sameo@openedhand.com>
  18. *
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/clk.h>
  22. #include <linux/slab.h>
  23. #include <linux/module.h>
  24. #include <linux/of_device.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/mmc/host.h>
  27. #include <linux/mmc/slot-gpio.h>
  28. #include <linux/mfd/tmio.h>
  29. #include <linux/sh_dma.h>
  30. #include <linux/delay.h>
  31. #include <linux/pinctrl/consumer.h>
  32. #include <linux/pinctrl/pinctrl-state.h>
  33. #include <linux/regulator/consumer.h>
  34. #include "renesas_sdhi.h"
  35. #include "tmio_mmc.h"
  36. #define HOST_MODE 0xe4
  37. #define SDHI_VER_GEN2_SDR50 0x490c
  38. #define SDHI_VER_RZ_A1 0x820b
  39. /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  40. #define SDHI_VER_GEN2_SDR104 0xcb0d
  41. #define SDHI_VER_GEN3_SD 0xcc10
  42. #define SDHI_VER_GEN3_SDMMC 0xcd10
  43. static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  44. {
  45. u32 val;
  46. /*
  47. * see also
  48. * renesas_sdhi_of_data :: dma_buswidth
  49. */
  50. switch (sd_ctrl_read16(host, CTL_VERSION)) {
  51. case SDHI_VER_GEN2_SDR50:
  52. val = (width == 32) ? 0x0001 : 0x0000;
  53. break;
  54. case SDHI_VER_GEN2_SDR104:
  55. val = (width == 32) ? 0x0000 : 0x0001;
  56. break;
  57. case SDHI_VER_GEN3_SD:
  58. case SDHI_VER_GEN3_SDMMC:
  59. if (width == 64)
  60. val = 0x0000;
  61. else if (width == 32)
  62. val = 0x0101;
  63. else
  64. val = 0x0001;
  65. break;
  66. default:
  67. /* nothing to do */
  68. return;
  69. }
  70. sd_ctrl_write16(host, HOST_MODE, val);
  71. }
  72. static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  73. {
  74. struct mmc_host *mmc = host->mmc;
  75. struct renesas_sdhi *priv = host_to_priv(host);
  76. int ret = clk_prepare_enable(priv->clk);
  77. if (ret < 0)
  78. return ret;
  79. ret = clk_prepare_enable(priv->clk_cd);
  80. if (ret < 0) {
  81. clk_disable_unprepare(priv->clk);
  82. return ret;
  83. }
  84. /*
  85. * The clock driver may not know what maximum frequency
  86. * actually works, so it should be set with the max-frequency
  87. * property which will already have been read to f_max. If it
  88. * was missing, assume the current frequency is the maximum.
  89. */
  90. if (!mmc->f_max)
  91. mmc->f_max = clk_get_rate(priv->clk);
  92. /*
  93. * Minimum frequency is the minimum input clock frequency
  94. * divided by our maximum divider.
  95. */
  96. mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
  97. /* enable 16bit data access on SDBUF as default */
  98. renesas_sdhi_sdbuf_width(host, 16);
  99. return 0;
  100. }
  101. static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
  102. unsigned int new_clock)
  103. {
  104. struct renesas_sdhi *priv = host_to_priv(host);
  105. unsigned int freq, diff, best_freq = 0, diff_min = ~0;
  106. int i, ret;
  107. /* tested only on R-Car Gen2+ currently; may work for others */
  108. if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
  109. return clk_get_rate(priv->clk);
  110. /*
  111. * We want the bus clock to be as close as possible to, but no
  112. * greater than, new_clock. As we can divide by 1 << i for
  113. * any i in [0, 9] we want the input clock to be as close as
  114. * possible, but no greater than, new_clock << i.
  115. */
  116. for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
  117. freq = clk_round_rate(priv->clk, new_clock << i);
  118. if (freq > (new_clock << i)) {
  119. /* Too fast; look for a slightly slower option */
  120. freq = clk_round_rate(priv->clk,
  121. (new_clock << i) / 4 * 3);
  122. if (freq > (new_clock << i))
  123. continue;
  124. }
  125. diff = new_clock - (freq >> i);
  126. if (diff <= diff_min) {
  127. best_freq = freq;
  128. diff_min = diff;
  129. }
  130. }
  131. ret = clk_set_rate(priv->clk, best_freq);
  132. return ret == 0 ? best_freq : clk_get_rate(priv->clk);
  133. }
  134. static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
  135. unsigned int new_clock)
  136. {
  137. u32 clk = 0, clock;
  138. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  139. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  140. if (new_clock == 0)
  141. goto out;
  142. /*
  143. * Both HS400 and HS200/SD104 set 200MHz, but some devices need to
  144. * set 400MHz to distinguish the CPG settings in HS400.
  145. */
  146. if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
  147. host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
  148. new_clock == 200000000)
  149. new_clock = 400000000;
  150. clock = renesas_sdhi_clk_update(host, new_clock) / 512;
  151. for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
  152. clock <<= 1;
  153. /* 1/1 clock is option */
  154. if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
  155. if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
  156. clk |= 0xff;
  157. else
  158. clk &= ~0xff;
  159. }
  160. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
  161. if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
  162. usleep_range(10000, 11000);
  163. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  164. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  165. out:
  166. /* HW engineers overrode docs: no sleep needed on R-Car2+ */
  167. if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
  168. usleep_range(10000, 11000);
  169. }
  170. static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
  171. {
  172. struct renesas_sdhi *priv = host_to_priv(host);
  173. clk_disable_unprepare(priv->clk);
  174. clk_disable_unprepare(priv->clk_cd);
  175. }
  176. static int renesas_sdhi_card_busy(struct mmc_host *mmc)
  177. {
  178. struct tmio_mmc_host *host = mmc_priv(mmc);
  179. return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
  180. TMIO_STAT_DAT0);
  181. }
  182. static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
  183. struct mmc_ios *ios)
  184. {
  185. struct tmio_mmc_host *host = mmc_priv(mmc);
  186. struct renesas_sdhi *priv = host_to_priv(host);
  187. struct pinctrl_state *pin_state;
  188. int ret;
  189. switch (ios->signal_voltage) {
  190. case MMC_SIGNAL_VOLTAGE_330:
  191. pin_state = priv->pins_default;
  192. break;
  193. case MMC_SIGNAL_VOLTAGE_180:
  194. pin_state = priv->pins_uhs;
  195. break;
  196. default:
  197. return -EINVAL;
  198. }
  199. /*
  200. * If anything is missing, assume signal voltage is fixed at
  201. * 3.3V and succeed/fail accordingly.
  202. */
  203. if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
  204. return ios->signal_voltage ==
  205. MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
  206. ret = mmc_regulator_set_vqmmc(host->mmc, ios);
  207. if (ret)
  208. return ret;
  209. return pinctrl_select_state(priv->pinctrl, pin_state);
  210. }
  211. /* SCC registers */
  212. #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
  213. #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
  214. #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
  215. #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
  216. #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
  217. #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
  218. #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
  219. /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
  220. #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
  221. #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
  222. #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
  223. /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
  224. #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
  225. /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
  226. #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
  227. /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
  228. #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
  229. /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */
  230. #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
  231. #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
  232. static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
  233. struct renesas_sdhi *priv, int addr)
  234. {
  235. return readl(priv->scc_ctl + (addr << host->bus_shift));
  236. }
  237. static inline void sd_scc_write32(struct tmio_mmc_host *host,
  238. struct renesas_sdhi *priv,
  239. int addr, u32 val)
  240. {
  241. writel(val, priv->scc_ctl + (addr << host->bus_shift));
  242. }
  243. static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
  244. {
  245. struct renesas_sdhi *priv;
  246. priv = host_to_priv(host);
  247. /* Initialize SCC */
  248. sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
  249. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  250. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  251. /* set sampling clock selection range */
  252. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
  253. SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
  254. 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
  255. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
  256. SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
  257. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
  258. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
  259. ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
  260. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
  261. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
  262. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  263. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  264. /* Read TAPNUM */
  265. return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
  266. SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
  267. SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
  268. }
  269. static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
  270. unsigned long tap)
  271. {
  272. struct renesas_sdhi *priv = host_to_priv(host);
  273. /* Set sampling clock position */
  274. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
  275. }
  276. static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host)
  277. {
  278. struct renesas_sdhi *priv = host_to_priv(host);
  279. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  280. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  281. /* Set HS400 mode */
  282. sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
  283. sd_ctrl_read16(host, CTL_SDIF_MODE));
  284. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
  285. (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
  286. SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
  287. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
  288. /* Set the sampling clock selection range of HS400 mode */
  289. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
  290. SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
  291. 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
  292. if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400)
  293. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
  294. host->tap_set / 2);
  295. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
  296. SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
  297. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
  298. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  299. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  300. }
  301. static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
  302. struct renesas_sdhi *priv)
  303. {
  304. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  305. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  306. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
  307. ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
  308. sd_scc_read32(host, priv,
  309. SH_MOBILE_SDHI_SCC_CKSEL));
  310. }
  311. static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host)
  312. {
  313. struct renesas_sdhi *priv = host_to_priv(host);
  314. renesas_sdhi_reset_scc(host, priv);
  315. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
  316. ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
  317. sd_scc_read32(host, priv,
  318. SH_MOBILE_SDHI_SCC_DTCNTL));
  319. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  320. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  321. }
  322. static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
  323. struct renesas_sdhi *priv)
  324. {
  325. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  326. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  327. /* Reset HS400 mode */
  328. sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
  329. sd_ctrl_read16(host, CTL_SDIF_MODE));
  330. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
  331. ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
  332. SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
  333. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
  334. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  335. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  336. }
  337. static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host)
  338. {
  339. renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
  340. }
  341. #define SH_MOBILE_SDHI_MAX_TAP 3
  342. static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
  343. {
  344. struct renesas_sdhi *priv = host_to_priv(host);
  345. unsigned long tap_cnt; /* counter of tuning success */
  346. unsigned long tap_start;/* start position of tuning success */
  347. unsigned long tap_end; /* end position of tuning success */
  348. unsigned long ntap; /* temporary counter of tuning success */
  349. unsigned long i;
  350. /* Clear SCC_RVSREQ */
  351. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
  352. /*
  353. * When tuning CMD19 is issued twice for each tap, merge the
  354. * result requiring the tap to be good in both runs before
  355. * considering it for tuning selection.
  356. */
  357. for (i = 0; i < host->tap_num * 2; i++) {
  358. int offset = host->tap_num * (i < host->tap_num ? 1 : -1);
  359. if (!test_bit(i, host->taps))
  360. clear_bit(i + offset, host->taps);
  361. }
  362. /*
  363. * Find the longest consecutive run of successful probes. If that
  364. * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
  365. * center index as the tap.
  366. */
  367. tap_cnt = 0;
  368. ntap = 0;
  369. tap_start = 0;
  370. tap_end = 0;
  371. for (i = 0; i < host->tap_num * 2; i++) {
  372. if (test_bit(i, host->taps)) {
  373. ntap++;
  374. } else {
  375. if (ntap > tap_cnt) {
  376. tap_start = i - ntap;
  377. tap_end = i - 1;
  378. tap_cnt = ntap;
  379. }
  380. ntap = 0;
  381. }
  382. }
  383. if (ntap > tap_cnt) {
  384. tap_start = i - ntap;
  385. tap_end = i - 1;
  386. tap_cnt = ntap;
  387. }
  388. if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
  389. host->tap_set = (tap_start + tap_end) / 2 % host->tap_num;
  390. else
  391. return -EIO;
  392. /* Set SCC */
  393. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set);
  394. /* Enable auto re-tuning */
  395. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
  396. SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
  397. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
  398. return 0;
  399. }
  400. static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
  401. {
  402. struct renesas_sdhi *priv = host_to_priv(host);
  403. bool use_4tap = host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400;
  404. /*
  405. * Skip checking SCC errors when running on 4 taps in HS400 mode as
  406. * any retuning would still result in the same 4 taps being used.
  407. */
  408. if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
  409. !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
  410. !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
  411. return false;
  412. if (mmc_doing_retune(host->mmc))
  413. return false;
  414. /* Check SCC error */
  415. if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
  416. SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
  417. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
  418. SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
  419. /* Clear SCC error */
  420. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
  421. return true;
  422. }
  423. return false;
  424. }
  425. static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
  426. {
  427. struct renesas_sdhi *priv;
  428. priv = host_to_priv(host);
  429. renesas_sdhi_reset_scc(host, priv);
  430. renesas_sdhi_reset_hs400_mode(host, priv);
  431. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  432. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  433. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
  434. ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
  435. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
  436. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
  437. ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
  438. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
  439. }
  440. static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
  441. {
  442. int timeout = 1000;
  443. /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
  444. u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
  445. while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
  446. & bit) == wait_state)
  447. udelay(1);
  448. if (!timeout) {
  449. dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
  450. return -EBUSY;
  451. }
  452. return 0;
  453. }
  454. static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
  455. {
  456. u32 bit = TMIO_STAT_SCLKDIVEN;
  457. switch (addr) {
  458. case CTL_SD_CMD:
  459. case CTL_STOP_INTERNAL_ACTION:
  460. case CTL_XFER_BLK_COUNT:
  461. case CTL_SD_XFER_LEN:
  462. case CTL_SD_MEM_CARD_OPT:
  463. case CTL_TRANSACTION_CTL:
  464. case CTL_DMA_ENABLE:
  465. case HOST_MODE:
  466. if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
  467. bit = TMIO_STAT_CMD_BUSY;
  468. /* fallthrough */
  469. case CTL_SD_CARD_CLK_CTL:
  470. return renesas_sdhi_wait_idle(host, bit);
  471. }
  472. return 0;
  473. }
  474. static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
  475. unsigned int direction, int blk_size)
  476. {
  477. /*
  478. * In Renesas controllers, when performing a
  479. * multiple block read of one or two blocks,
  480. * depending on the timing with which the
  481. * response register is read, the response
  482. * value may not be read properly.
  483. * Use single block read for this HW bug
  484. */
  485. if ((direction == MMC_DATA_READ) &&
  486. blk_size == 2)
  487. return 1;
  488. return blk_size;
  489. }
  490. static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
  491. {
  492. /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
  493. int width = (host->bus_shift == 2) ? 64 : 32;
  494. sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
  495. renesas_sdhi_sdbuf_width(host, enable ? width : 16);
  496. }
  497. int renesas_sdhi_probe(struct platform_device *pdev,
  498. const struct tmio_mmc_dma_ops *dma_ops)
  499. {
  500. struct tmio_mmc_data *mmd = pdev->dev.platform_data;
  501. const struct renesas_sdhi_of_data *of_data;
  502. struct tmio_mmc_data *mmc_data;
  503. struct tmio_mmc_dma *dma_priv;
  504. struct tmio_mmc_host *host;
  505. struct renesas_sdhi *priv;
  506. struct resource *res;
  507. int irq, ret, i;
  508. of_data = of_device_get_match_data(&pdev->dev);
  509. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  510. if (!res)
  511. return -EINVAL;
  512. priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
  513. GFP_KERNEL);
  514. if (!priv)
  515. return -ENOMEM;
  516. mmc_data = &priv->mmc_data;
  517. dma_priv = &priv->dma_priv;
  518. priv->clk = devm_clk_get(&pdev->dev, NULL);
  519. if (IS_ERR(priv->clk)) {
  520. ret = PTR_ERR(priv->clk);
  521. dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
  522. return ret;
  523. }
  524. /*
  525. * Some controllers provide a 2nd clock just to run the internal card
  526. * detection logic. Unfortunately, the existing driver architecture does
  527. * not support a separation of clocks for runtime PM usage. When
  528. * native hotplug is used, the tmio driver assumes that the core
  529. * must continue to run for card detect to stay active, so we cannot
  530. * disable it.
  531. * Additionally, it is prohibited to supply a clock to the core but not
  532. * to the card detect circuit. That leaves us with if separate clocks
  533. * are presented, we must treat them both as virtually 1 clock.
  534. */
  535. priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
  536. if (IS_ERR(priv->clk_cd))
  537. priv->clk_cd = NULL;
  538. priv->pinctrl = devm_pinctrl_get(&pdev->dev);
  539. if (!IS_ERR(priv->pinctrl)) {
  540. priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
  541. PINCTRL_STATE_DEFAULT);
  542. priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
  543. "state_uhs");
  544. }
  545. host = tmio_mmc_host_alloc(pdev, mmc_data);
  546. if (IS_ERR(host))
  547. return PTR_ERR(host);
  548. if (of_data) {
  549. mmc_data->flags |= of_data->tmio_flags;
  550. mmc_data->ocr_mask = of_data->tmio_ocr_mask;
  551. mmc_data->capabilities |= of_data->capabilities;
  552. mmc_data->capabilities2 |= of_data->capabilities2;
  553. mmc_data->dma_rx_offset = of_data->dma_rx_offset;
  554. mmc_data->max_blk_count = of_data->max_blk_count;
  555. mmc_data->max_segs = of_data->max_segs;
  556. dma_priv->dma_buswidth = of_data->dma_buswidth;
  557. host->bus_shift = of_data->bus_shift;
  558. }
  559. host->write16_hook = renesas_sdhi_write16_hook;
  560. host->clk_enable = renesas_sdhi_clk_enable;
  561. host->clk_disable = renesas_sdhi_clk_disable;
  562. host->set_clock = renesas_sdhi_set_clock;
  563. host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
  564. host->dma_ops = dma_ops;
  565. /* For some SoC, we disable internal WP. GPIO may override this */
  566. if (mmc_can_gpio_ro(host->mmc))
  567. mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
  568. /* SDR speeds are only available on Gen2+ */
  569. if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
  570. /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
  571. host->ops.card_busy = renesas_sdhi_card_busy;
  572. host->ops.start_signal_voltage_switch =
  573. renesas_sdhi_start_signal_voltage_switch;
  574. }
  575. /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
  576. if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
  577. host->bus_shift = 1;
  578. if (mmd)
  579. *mmc_data = *mmd;
  580. dma_priv->filter = shdma_chan_filter;
  581. dma_priv->enable = renesas_sdhi_enable_dma;
  582. mmc_data->alignment_shift = 1; /* 2-byte alignment */
  583. mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
  584. /*
  585. * All SDHI blocks support 2-byte and larger block sizes in 4-bit
  586. * bus width mode.
  587. */
  588. mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
  589. /*
  590. * All SDHI blocks support SDIO IRQ signalling.
  591. */
  592. mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
  593. /* All SDHI have CMD12 control bit */
  594. mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
  595. /* All SDHI have SDIO status bits which must be 1 */
  596. mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
  597. ret = renesas_sdhi_clk_enable(host);
  598. if (ret)
  599. goto efree;
  600. ret = tmio_mmc_host_probe(host);
  601. if (ret < 0)
  602. goto edisclk;
  603. /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
  604. if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50)
  605. mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
  606. /* Enable tuning iff we have an SCC and a supported mode */
  607. if (of_data && of_data->scc_offset &&
  608. (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
  609. host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
  610. MMC_CAP2_HS400_1_8V))) {
  611. const struct renesas_sdhi_scc *taps = of_data->taps;
  612. bool hit = false;
  613. host->mmc->caps |= MMC_CAP_HW_RESET;
  614. for (i = 0; i < of_data->taps_num; i++) {
  615. if (taps[i].clk_rate == 0 ||
  616. taps[i].clk_rate == host->mmc->f_max) {
  617. priv->scc_tappos = taps->tap;
  618. hit = true;
  619. break;
  620. }
  621. }
  622. if (!hit)
  623. dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
  624. priv->scc_ctl = host->ctl + of_data->scc_offset;
  625. host->init_tuning = renesas_sdhi_init_tuning;
  626. host->prepare_tuning = renesas_sdhi_prepare_tuning;
  627. host->select_tuning = renesas_sdhi_select_tuning;
  628. host->check_scc_error = renesas_sdhi_check_scc_error;
  629. host->hw_reset = renesas_sdhi_hw_reset;
  630. host->prepare_hs400_tuning =
  631. renesas_sdhi_prepare_hs400_tuning;
  632. host->hs400_downgrade = renesas_sdhi_disable_scc;
  633. host->hs400_complete = renesas_sdhi_hs400_complete;
  634. }
  635. i = 0;
  636. while (1) {
  637. irq = platform_get_irq(pdev, i);
  638. if (irq < 0)
  639. break;
  640. i++;
  641. ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
  642. dev_name(&pdev->dev), host);
  643. if (ret)
  644. goto eirq;
  645. }
  646. /* There must be at least one IRQ source */
  647. if (!i) {
  648. ret = irq;
  649. goto eirq;
  650. }
  651. dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
  652. mmc_hostname(host->mmc), (unsigned long)
  653. (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
  654. host->mmc->f_max / 1000000);
  655. return ret;
  656. eirq:
  657. tmio_mmc_host_remove(host);
  658. edisclk:
  659. renesas_sdhi_clk_disable(host);
  660. efree:
  661. tmio_mmc_host_free(host);
  662. return ret;
  663. }
  664. EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
  665. int renesas_sdhi_remove(struct platform_device *pdev)
  666. {
  667. struct tmio_mmc_host *host = platform_get_drvdata(pdev);
  668. tmio_mmc_host_remove(host);
  669. renesas_sdhi_clk_disable(host);
  670. return 0;
  671. }
  672. EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
  673. MODULE_LICENSE("GPL v2");