scif_main.c 8.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359
  1. /*
  2. * Intel MIC Platform Software Stack (MPSS)
  3. *
  4. * Copyright(c) 2014 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License, version 2, as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * Intel SCIF driver.
  16. *
  17. */
  18. #include <linux/module.h>
  19. #include <linux/idr.h>
  20. #include <linux/mic_common.h>
  21. #include "../common/mic_dev.h"
  22. #include "../bus/scif_bus.h"
  23. #include "scif_peer_bus.h"
  24. #include "scif_main.h"
  25. #include "scif_map.h"
  26. struct scif_info scif_info = {
  27. .mdev = {
  28. .minor = MISC_DYNAMIC_MINOR,
  29. .name = "scif",
  30. .fops = &scif_fops,
  31. }
  32. };
  33. struct scif_dev *scif_dev;
  34. struct kmem_cache *unaligned_cache;
  35. static atomic_t g_loopb_cnt;
  36. /* Runs in the context of intr_wq */
  37. static void scif_intr_bh_handler(struct work_struct *work)
  38. {
  39. struct scif_dev *scifdev =
  40. container_of(work, struct scif_dev, intr_bh);
  41. if (scifdev_self(scifdev))
  42. scif_loopb_msg_handler(scifdev, scifdev->qpairs);
  43. else
  44. scif_nodeqp_intrhandler(scifdev, scifdev->qpairs);
  45. }
  46. int scif_setup_intr_wq(struct scif_dev *scifdev)
  47. {
  48. if (!scifdev->intr_wq) {
  49. snprintf(scifdev->intr_wqname, sizeof(scifdev->intr_wqname),
  50. "SCIF INTR %d", scifdev->node);
  51. scifdev->intr_wq =
  52. alloc_ordered_workqueue(scifdev->intr_wqname, 0);
  53. if (!scifdev->intr_wq)
  54. return -ENOMEM;
  55. INIT_WORK(&scifdev->intr_bh, scif_intr_bh_handler);
  56. }
  57. return 0;
  58. }
  59. void scif_destroy_intr_wq(struct scif_dev *scifdev)
  60. {
  61. if (scifdev->intr_wq) {
  62. destroy_workqueue(scifdev->intr_wq);
  63. scifdev->intr_wq = NULL;
  64. }
  65. }
  66. irqreturn_t scif_intr_handler(int irq, void *data)
  67. {
  68. struct scif_dev *scifdev = data;
  69. struct scif_hw_dev *sdev = scifdev->sdev;
  70. sdev->hw_ops->ack_interrupt(sdev, scifdev->db);
  71. queue_work(scifdev->intr_wq, &scifdev->intr_bh);
  72. return IRQ_HANDLED;
  73. }
  74. static void scif_qp_setup_handler(struct work_struct *work)
  75. {
  76. struct scif_dev *scifdev = container_of(work, struct scif_dev,
  77. qp_dwork.work);
  78. struct scif_hw_dev *sdev = scifdev->sdev;
  79. dma_addr_t da = 0;
  80. int err;
  81. if (scif_is_mgmt_node()) {
  82. struct mic_bootparam *bp = sdev->dp;
  83. da = bp->scif_card_dma_addr;
  84. scifdev->rdb = bp->h2c_scif_db;
  85. } else {
  86. struct mic_bootparam __iomem *bp = sdev->rdp;
  87. da = readq(&bp->scif_host_dma_addr);
  88. scifdev->rdb = ioread8(&bp->c2h_scif_db);
  89. }
  90. if (da) {
  91. err = scif_qp_response(da, scifdev);
  92. if (err)
  93. dev_err(&scifdev->sdev->dev,
  94. "scif_qp_response err %d\n", err);
  95. } else {
  96. schedule_delayed_work(&scifdev->qp_dwork,
  97. msecs_to_jiffies(1000));
  98. }
  99. }
  100. static int scif_setup_scifdev(void)
  101. {
  102. /* We support a maximum of 129 SCIF nodes including the mgmt node */
  103. #define MAX_SCIF_NODES 129
  104. int i;
  105. u8 num_nodes = MAX_SCIF_NODES;
  106. scif_dev = kcalloc(num_nodes, sizeof(*scif_dev), GFP_KERNEL);
  107. if (!scif_dev)
  108. return -ENOMEM;
  109. for (i = 0; i < num_nodes; i++) {
  110. struct scif_dev *scifdev = &scif_dev[i];
  111. scifdev->node = i;
  112. scifdev->exit = OP_IDLE;
  113. init_waitqueue_head(&scifdev->disconn_wq);
  114. mutex_init(&scifdev->lock);
  115. INIT_WORK(&scifdev->peer_add_work, scif_add_peer_device);
  116. INIT_DELAYED_WORK(&scifdev->p2p_dwork,
  117. scif_poll_qp_state);
  118. INIT_DELAYED_WORK(&scifdev->qp_dwork,
  119. scif_qp_setup_handler);
  120. INIT_LIST_HEAD(&scifdev->p2p);
  121. RCU_INIT_POINTER(scifdev->spdev, NULL);
  122. }
  123. return 0;
  124. }
  125. static void scif_destroy_scifdev(void)
  126. {
  127. kfree(scif_dev);
  128. }
  129. static int scif_probe(struct scif_hw_dev *sdev)
  130. {
  131. struct scif_dev *scifdev = &scif_dev[sdev->dnode];
  132. int rc;
  133. dev_set_drvdata(&sdev->dev, sdev);
  134. scifdev->sdev = sdev;
  135. if (1 == atomic_add_return(1, &g_loopb_cnt)) {
  136. struct scif_dev *loopb_dev = &scif_dev[sdev->snode];
  137. loopb_dev->sdev = sdev;
  138. rc = scif_setup_loopback_qp(loopb_dev);
  139. if (rc)
  140. goto exit;
  141. }
  142. rc = scif_setup_intr_wq(scifdev);
  143. if (rc)
  144. goto destroy_loopb;
  145. rc = scif_setup_qp(scifdev);
  146. if (rc)
  147. goto destroy_intr;
  148. scifdev->db = sdev->hw_ops->next_db(sdev);
  149. scifdev->cookie = sdev->hw_ops->request_irq(sdev, scif_intr_handler,
  150. "SCIF_INTR", scifdev,
  151. scifdev->db);
  152. if (IS_ERR(scifdev->cookie)) {
  153. rc = PTR_ERR(scifdev->cookie);
  154. goto free_qp;
  155. }
  156. if (scif_is_mgmt_node()) {
  157. struct mic_bootparam *bp = sdev->dp;
  158. bp->c2h_scif_db = scifdev->db;
  159. bp->scif_host_dma_addr = scifdev->qp_dma_addr;
  160. } else {
  161. struct mic_bootparam __iomem *bp = sdev->rdp;
  162. iowrite8(scifdev->db, &bp->h2c_scif_db);
  163. writeq(scifdev->qp_dma_addr, &bp->scif_card_dma_addr);
  164. }
  165. schedule_delayed_work(&scifdev->qp_dwork,
  166. msecs_to_jiffies(1000));
  167. return rc;
  168. free_qp:
  169. scif_free_qp(scifdev);
  170. destroy_intr:
  171. scif_destroy_intr_wq(scifdev);
  172. destroy_loopb:
  173. if (atomic_dec_and_test(&g_loopb_cnt))
  174. scif_destroy_loopback_qp(&scif_dev[sdev->snode]);
  175. exit:
  176. return rc;
  177. }
  178. void scif_stop(struct scif_dev *scifdev)
  179. {
  180. struct scif_dev *dev;
  181. int i;
  182. for (i = scif_info.maxid; i >= 0; i--) {
  183. dev = &scif_dev[i];
  184. if (scifdev_self(dev))
  185. continue;
  186. scif_handle_remove_node(i);
  187. }
  188. }
  189. static void scif_remove(struct scif_hw_dev *sdev)
  190. {
  191. struct scif_dev *scifdev = &scif_dev[sdev->dnode];
  192. if (scif_is_mgmt_node()) {
  193. struct mic_bootparam *bp = sdev->dp;
  194. bp->c2h_scif_db = -1;
  195. bp->scif_host_dma_addr = 0x0;
  196. } else {
  197. struct mic_bootparam __iomem *bp = sdev->rdp;
  198. iowrite8(-1, &bp->h2c_scif_db);
  199. writeq(0x0, &bp->scif_card_dma_addr);
  200. }
  201. if (scif_is_mgmt_node()) {
  202. scif_disconnect_node(scifdev->node, true);
  203. } else {
  204. scif_info.card_initiated_exit = true;
  205. scif_stop(scifdev);
  206. }
  207. if (atomic_dec_and_test(&g_loopb_cnt))
  208. scif_destroy_loopback_qp(&scif_dev[sdev->snode]);
  209. if (scifdev->cookie) {
  210. sdev->hw_ops->free_irq(sdev, scifdev->cookie, scifdev);
  211. scifdev->cookie = NULL;
  212. }
  213. scif_destroy_intr_wq(scifdev);
  214. cancel_delayed_work(&scifdev->qp_dwork);
  215. scif_free_qp(scifdev);
  216. scifdev->rdb = -1;
  217. scifdev->sdev = NULL;
  218. }
  219. static struct scif_hw_dev_id id_table[] = {
  220. { MIC_SCIF_DEV, SCIF_DEV_ANY_ID },
  221. { 0 },
  222. };
  223. static struct scif_driver scif_driver = {
  224. .driver.name = KBUILD_MODNAME,
  225. .driver.owner = THIS_MODULE,
  226. .id_table = id_table,
  227. .probe = scif_probe,
  228. .remove = scif_remove,
  229. };
  230. static int _scif_init(void)
  231. {
  232. int rc;
  233. mutex_init(&scif_info.eplock);
  234. spin_lock_init(&scif_info.rmalock);
  235. spin_lock_init(&scif_info.nb_connect_lock);
  236. spin_lock_init(&scif_info.port_lock);
  237. mutex_init(&scif_info.conflock);
  238. mutex_init(&scif_info.connlock);
  239. mutex_init(&scif_info.fencelock);
  240. INIT_LIST_HEAD(&scif_info.uaccept);
  241. INIT_LIST_HEAD(&scif_info.listen);
  242. INIT_LIST_HEAD(&scif_info.zombie);
  243. INIT_LIST_HEAD(&scif_info.connected);
  244. INIT_LIST_HEAD(&scif_info.disconnected);
  245. INIT_LIST_HEAD(&scif_info.rma);
  246. INIT_LIST_HEAD(&scif_info.rma_tc);
  247. INIT_LIST_HEAD(&scif_info.mmu_notif_cleanup);
  248. INIT_LIST_HEAD(&scif_info.fence);
  249. INIT_LIST_HEAD(&scif_info.nb_connect_list);
  250. init_waitqueue_head(&scif_info.exitwq);
  251. scif_info.rma_tc_limit = SCIF_RMA_TEMP_CACHE_LIMIT;
  252. scif_info.en_msg_log = 0;
  253. scif_info.p2p_enable = 1;
  254. rc = scif_setup_scifdev();
  255. if (rc)
  256. goto error;
  257. unaligned_cache = kmem_cache_create("Unaligned_DMA",
  258. SCIF_KMEM_UNALIGNED_BUF_SIZE,
  259. 0, SLAB_HWCACHE_ALIGN, NULL);
  260. if (!unaligned_cache) {
  261. rc = -ENOMEM;
  262. goto free_sdev;
  263. }
  264. INIT_WORK(&scif_info.misc_work, scif_misc_handler);
  265. INIT_WORK(&scif_info.mmu_notif_work, scif_mmu_notif_handler);
  266. INIT_WORK(&scif_info.conn_work, scif_conn_handler);
  267. idr_init(&scif_ports);
  268. return 0;
  269. free_sdev:
  270. scif_destroy_scifdev();
  271. error:
  272. return rc;
  273. }
  274. static void _scif_exit(void)
  275. {
  276. idr_destroy(&scif_ports);
  277. kmem_cache_destroy(unaligned_cache);
  278. scif_destroy_scifdev();
  279. }
  280. static int __init scif_init(void)
  281. {
  282. struct miscdevice *mdev = &scif_info.mdev;
  283. int rc;
  284. _scif_init();
  285. iova_cache_get();
  286. rc = scif_peer_bus_init();
  287. if (rc)
  288. goto exit;
  289. rc = scif_register_driver(&scif_driver);
  290. if (rc)
  291. goto peer_bus_exit;
  292. rc = misc_register(mdev);
  293. if (rc)
  294. goto unreg_scif;
  295. scif_init_debugfs();
  296. return 0;
  297. unreg_scif:
  298. scif_unregister_driver(&scif_driver);
  299. peer_bus_exit:
  300. scif_peer_bus_exit();
  301. exit:
  302. _scif_exit();
  303. return rc;
  304. }
  305. static void __exit scif_exit(void)
  306. {
  307. scif_exit_debugfs();
  308. misc_deregister(&scif_info.mdev);
  309. scif_unregister_driver(&scif_driver);
  310. scif_peer_bus_exit();
  311. iova_cache_put();
  312. _scif_exit();
  313. }
  314. module_init(scif_init);
  315. module_exit(scif_exit);
  316. MODULE_DEVICE_TABLE(scif, id_table);
  317. MODULE_AUTHOR("Intel Corporation");
  318. MODULE_DESCRIPTION("Intel(R) SCIF driver");
  319. MODULE_LICENSE("GPL v2");