pvrdma_main.c 32 KB

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  1. /*
  2. * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of EITHER the GNU General Public License
  6. * version 2 as published by the Free Software Foundation or the BSD
  7. * 2-Clause License. This program is distributed in the hope that it
  8. * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
  9. * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
  10. * See the GNU General Public License version 2 for more details at
  11. * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program available in the file COPYING in the main
  15. * directory of this source tree.
  16. *
  17. * The BSD 2-Clause License
  18. *
  19. * Redistribution and use in source and binary forms, with or
  20. * without modification, are permitted provided that the following
  21. * conditions are met:
  22. *
  23. * - Redistributions of source code must retain the above
  24. * copyright notice, this list of conditions and the following
  25. * disclaimer.
  26. *
  27. * - Redistributions in binary form must reproduce the above
  28. * copyright notice, this list of conditions and the following
  29. * disclaimer in the documentation and/or other materials
  30. * provided with the distribution.
  31. *
  32. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  33. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  34. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  35. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  36. * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  37. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  38. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  39. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  40. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  41. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  42. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  43. * OF THE POSSIBILITY OF SUCH DAMAGE.
  44. */
  45. #include <linux/errno.h>
  46. #include <linux/inetdevice.h>
  47. #include <linux/init.h>
  48. #include <linux/module.h>
  49. #include <linux/slab.h>
  50. #include <rdma/ib_addr.h>
  51. #include <rdma/ib_smi.h>
  52. #include <rdma/ib_user_verbs.h>
  53. #include <net/addrconf.h>
  54. #include "pvrdma.h"
  55. #define DRV_NAME "vmw_pvrdma"
  56. #define DRV_VERSION "1.0.1.0-k"
  57. static DEFINE_MUTEX(pvrdma_device_list_lock);
  58. static LIST_HEAD(pvrdma_device_list);
  59. static struct workqueue_struct *event_wq;
  60. static int pvrdma_add_gid(const struct ib_gid_attr *attr, void **context);
  61. static int pvrdma_del_gid(const struct ib_gid_attr *attr, void **context);
  62. static ssize_t hca_type_show(struct device *device,
  63. struct device_attribute *attr, char *buf)
  64. {
  65. return sprintf(buf, "VMW_PVRDMA-%s\n", DRV_VERSION);
  66. }
  67. static DEVICE_ATTR_RO(hca_type);
  68. static ssize_t hw_rev_show(struct device *device,
  69. struct device_attribute *attr, char *buf)
  70. {
  71. return sprintf(buf, "%d\n", PVRDMA_REV_ID);
  72. }
  73. static DEVICE_ATTR_RO(hw_rev);
  74. static ssize_t board_id_show(struct device *device,
  75. struct device_attribute *attr, char *buf)
  76. {
  77. return sprintf(buf, "%d\n", PVRDMA_BOARD_ID);
  78. }
  79. static DEVICE_ATTR_RO(board_id);
  80. static struct attribute *pvrdma_class_attributes[] = {
  81. &dev_attr_hw_rev.attr,
  82. &dev_attr_hca_type.attr,
  83. &dev_attr_board_id.attr,
  84. NULL,
  85. };
  86. static const struct attribute_group pvrdma_attr_group = {
  87. .attrs = pvrdma_class_attributes,
  88. };
  89. static void pvrdma_get_fw_ver_str(struct ib_device *device, char *str)
  90. {
  91. struct pvrdma_dev *dev =
  92. container_of(device, struct pvrdma_dev, ib_dev);
  93. snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d\n",
  94. (int) (dev->dsr->caps.fw_ver >> 32),
  95. (int) (dev->dsr->caps.fw_ver >> 16) & 0xffff,
  96. (int) dev->dsr->caps.fw_ver & 0xffff);
  97. }
  98. static int pvrdma_init_device(struct pvrdma_dev *dev)
  99. {
  100. /* Initialize some device related stuff */
  101. spin_lock_init(&dev->cmd_lock);
  102. sema_init(&dev->cmd_sema, 1);
  103. atomic_set(&dev->num_qps, 0);
  104. atomic_set(&dev->num_srqs, 0);
  105. atomic_set(&dev->num_cqs, 0);
  106. atomic_set(&dev->num_pds, 0);
  107. atomic_set(&dev->num_ahs, 0);
  108. return 0;
  109. }
  110. static int pvrdma_port_immutable(struct ib_device *ibdev, u8 port_num,
  111. struct ib_port_immutable *immutable)
  112. {
  113. struct pvrdma_dev *dev = to_vdev(ibdev);
  114. struct ib_port_attr attr;
  115. int err;
  116. if (dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1)
  117. immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE;
  118. else if (dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V2)
  119. immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  120. err = ib_query_port(ibdev, port_num, &attr);
  121. if (err)
  122. return err;
  123. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  124. immutable->gid_tbl_len = attr.gid_tbl_len;
  125. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  126. return 0;
  127. }
  128. static struct net_device *pvrdma_get_netdev(struct ib_device *ibdev,
  129. u8 port_num)
  130. {
  131. struct net_device *netdev;
  132. struct pvrdma_dev *dev = to_vdev(ibdev);
  133. if (port_num != 1)
  134. return NULL;
  135. rcu_read_lock();
  136. netdev = dev->netdev;
  137. if (netdev)
  138. dev_hold(netdev);
  139. rcu_read_unlock();
  140. return netdev;
  141. }
  142. static int pvrdma_register_device(struct pvrdma_dev *dev)
  143. {
  144. int ret = -1;
  145. dev->ib_dev.node_guid = dev->dsr->caps.node_guid;
  146. dev->sys_image_guid = dev->dsr->caps.sys_image_guid;
  147. dev->flags = 0;
  148. dev->ib_dev.owner = THIS_MODULE;
  149. dev->ib_dev.num_comp_vectors = 1;
  150. dev->ib_dev.dev.parent = &dev->pdev->dev;
  151. dev->ib_dev.uverbs_abi_ver = PVRDMA_UVERBS_ABI_VERSION;
  152. dev->ib_dev.uverbs_cmd_mask =
  153. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  154. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  155. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  156. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  157. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  158. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  159. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  160. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  161. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  162. (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
  163. (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
  164. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  165. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  166. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  167. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  168. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  169. (1ull << IB_USER_VERBS_CMD_POST_SEND) |
  170. (1ull << IB_USER_VERBS_CMD_POST_RECV) |
  171. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  172. (1ull << IB_USER_VERBS_CMD_DESTROY_AH);
  173. dev->ib_dev.node_type = RDMA_NODE_IB_CA;
  174. dev->ib_dev.phys_port_cnt = dev->dsr->caps.phys_port_cnt;
  175. dev->ib_dev.query_device = pvrdma_query_device;
  176. dev->ib_dev.query_port = pvrdma_query_port;
  177. dev->ib_dev.query_gid = pvrdma_query_gid;
  178. dev->ib_dev.query_pkey = pvrdma_query_pkey;
  179. dev->ib_dev.modify_port = pvrdma_modify_port;
  180. dev->ib_dev.alloc_ucontext = pvrdma_alloc_ucontext;
  181. dev->ib_dev.dealloc_ucontext = pvrdma_dealloc_ucontext;
  182. dev->ib_dev.mmap = pvrdma_mmap;
  183. dev->ib_dev.alloc_pd = pvrdma_alloc_pd;
  184. dev->ib_dev.dealloc_pd = pvrdma_dealloc_pd;
  185. dev->ib_dev.create_ah = pvrdma_create_ah;
  186. dev->ib_dev.destroy_ah = pvrdma_destroy_ah;
  187. dev->ib_dev.create_qp = pvrdma_create_qp;
  188. dev->ib_dev.modify_qp = pvrdma_modify_qp;
  189. dev->ib_dev.query_qp = pvrdma_query_qp;
  190. dev->ib_dev.destroy_qp = pvrdma_destroy_qp;
  191. dev->ib_dev.post_send = pvrdma_post_send;
  192. dev->ib_dev.post_recv = pvrdma_post_recv;
  193. dev->ib_dev.create_cq = pvrdma_create_cq;
  194. dev->ib_dev.destroy_cq = pvrdma_destroy_cq;
  195. dev->ib_dev.poll_cq = pvrdma_poll_cq;
  196. dev->ib_dev.req_notify_cq = pvrdma_req_notify_cq;
  197. dev->ib_dev.get_dma_mr = pvrdma_get_dma_mr;
  198. dev->ib_dev.reg_user_mr = pvrdma_reg_user_mr;
  199. dev->ib_dev.dereg_mr = pvrdma_dereg_mr;
  200. dev->ib_dev.alloc_mr = pvrdma_alloc_mr;
  201. dev->ib_dev.map_mr_sg = pvrdma_map_mr_sg;
  202. dev->ib_dev.add_gid = pvrdma_add_gid;
  203. dev->ib_dev.del_gid = pvrdma_del_gid;
  204. dev->ib_dev.get_netdev = pvrdma_get_netdev;
  205. dev->ib_dev.get_port_immutable = pvrdma_port_immutable;
  206. dev->ib_dev.get_link_layer = pvrdma_port_link_layer;
  207. dev->ib_dev.get_dev_fw_str = pvrdma_get_fw_ver_str;
  208. mutex_init(&dev->port_mutex);
  209. spin_lock_init(&dev->desc_lock);
  210. dev->cq_tbl = kcalloc(dev->dsr->caps.max_cq, sizeof(struct pvrdma_cq *),
  211. GFP_KERNEL);
  212. if (!dev->cq_tbl)
  213. return ret;
  214. spin_lock_init(&dev->cq_tbl_lock);
  215. dev->qp_tbl = kcalloc(dev->dsr->caps.max_qp, sizeof(struct pvrdma_qp *),
  216. GFP_KERNEL);
  217. if (!dev->qp_tbl)
  218. goto err_cq_free;
  219. spin_lock_init(&dev->qp_tbl_lock);
  220. /* Check if SRQ is supported by backend */
  221. if (dev->dsr->caps.max_srq) {
  222. dev->ib_dev.uverbs_cmd_mask |=
  223. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  224. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  225. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  226. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  227. (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
  228. dev->ib_dev.create_srq = pvrdma_create_srq;
  229. dev->ib_dev.modify_srq = pvrdma_modify_srq;
  230. dev->ib_dev.query_srq = pvrdma_query_srq;
  231. dev->ib_dev.destroy_srq = pvrdma_destroy_srq;
  232. dev->srq_tbl = kcalloc(dev->dsr->caps.max_srq,
  233. sizeof(struct pvrdma_srq *),
  234. GFP_KERNEL);
  235. if (!dev->srq_tbl)
  236. goto err_qp_free;
  237. }
  238. dev->ib_dev.driver_id = RDMA_DRIVER_VMW_PVRDMA;
  239. spin_lock_init(&dev->srq_tbl_lock);
  240. rdma_set_device_sysfs_group(&dev->ib_dev, &pvrdma_attr_group);
  241. ret = ib_register_device(&dev->ib_dev, "vmw_pvrdma%d", NULL);
  242. if (ret)
  243. goto err_srq_free;
  244. dev->ib_active = true;
  245. return 0;
  246. err_srq_free:
  247. kfree(dev->srq_tbl);
  248. err_qp_free:
  249. kfree(dev->qp_tbl);
  250. err_cq_free:
  251. kfree(dev->cq_tbl);
  252. return ret;
  253. }
  254. static irqreturn_t pvrdma_intr0_handler(int irq, void *dev_id)
  255. {
  256. u32 icr = PVRDMA_INTR_CAUSE_RESPONSE;
  257. struct pvrdma_dev *dev = dev_id;
  258. dev_dbg(&dev->pdev->dev, "interrupt 0 (response) handler\n");
  259. if (!dev->pdev->msix_enabled) {
  260. /* Legacy intr */
  261. icr = pvrdma_read_reg(dev, PVRDMA_REG_ICR);
  262. if (icr == 0)
  263. return IRQ_NONE;
  264. }
  265. if (icr == PVRDMA_INTR_CAUSE_RESPONSE)
  266. complete(&dev->cmd_done);
  267. return IRQ_HANDLED;
  268. }
  269. static void pvrdma_qp_event(struct pvrdma_dev *dev, u32 qpn, int type)
  270. {
  271. struct pvrdma_qp *qp;
  272. unsigned long flags;
  273. spin_lock_irqsave(&dev->qp_tbl_lock, flags);
  274. qp = dev->qp_tbl[qpn % dev->dsr->caps.max_qp];
  275. if (qp)
  276. refcount_inc(&qp->refcnt);
  277. spin_unlock_irqrestore(&dev->qp_tbl_lock, flags);
  278. if (qp && qp->ibqp.event_handler) {
  279. struct ib_qp *ibqp = &qp->ibqp;
  280. struct ib_event e;
  281. e.device = ibqp->device;
  282. e.element.qp = ibqp;
  283. e.event = type; /* 1:1 mapping for now. */
  284. ibqp->event_handler(&e, ibqp->qp_context);
  285. }
  286. if (qp) {
  287. if (refcount_dec_and_test(&qp->refcnt))
  288. complete(&qp->free);
  289. }
  290. }
  291. static void pvrdma_cq_event(struct pvrdma_dev *dev, u32 cqn, int type)
  292. {
  293. struct pvrdma_cq *cq;
  294. unsigned long flags;
  295. spin_lock_irqsave(&dev->cq_tbl_lock, flags);
  296. cq = dev->cq_tbl[cqn % dev->dsr->caps.max_cq];
  297. if (cq)
  298. refcount_inc(&cq->refcnt);
  299. spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
  300. if (cq && cq->ibcq.event_handler) {
  301. struct ib_cq *ibcq = &cq->ibcq;
  302. struct ib_event e;
  303. e.device = ibcq->device;
  304. e.element.cq = ibcq;
  305. e.event = type; /* 1:1 mapping for now. */
  306. ibcq->event_handler(&e, ibcq->cq_context);
  307. }
  308. if (cq) {
  309. if (refcount_dec_and_test(&cq->refcnt))
  310. complete(&cq->free);
  311. }
  312. }
  313. static void pvrdma_srq_event(struct pvrdma_dev *dev, u32 srqn, int type)
  314. {
  315. struct pvrdma_srq *srq;
  316. unsigned long flags;
  317. spin_lock_irqsave(&dev->srq_tbl_lock, flags);
  318. if (dev->srq_tbl)
  319. srq = dev->srq_tbl[srqn % dev->dsr->caps.max_srq];
  320. else
  321. srq = NULL;
  322. if (srq)
  323. refcount_inc(&srq->refcnt);
  324. spin_unlock_irqrestore(&dev->srq_tbl_lock, flags);
  325. if (srq && srq->ibsrq.event_handler) {
  326. struct ib_srq *ibsrq = &srq->ibsrq;
  327. struct ib_event e;
  328. e.device = ibsrq->device;
  329. e.element.srq = ibsrq;
  330. e.event = type; /* 1:1 mapping for now. */
  331. ibsrq->event_handler(&e, ibsrq->srq_context);
  332. }
  333. if (srq) {
  334. if (refcount_dec_and_test(&srq->refcnt))
  335. complete(&srq->free);
  336. }
  337. }
  338. static void pvrdma_dispatch_event(struct pvrdma_dev *dev, int port,
  339. enum ib_event_type event)
  340. {
  341. struct ib_event ib_event;
  342. memset(&ib_event, 0, sizeof(ib_event));
  343. ib_event.device = &dev->ib_dev;
  344. ib_event.element.port_num = port;
  345. ib_event.event = event;
  346. ib_dispatch_event(&ib_event);
  347. }
  348. static void pvrdma_dev_event(struct pvrdma_dev *dev, u8 port, int type)
  349. {
  350. if (port < 1 || port > dev->dsr->caps.phys_port_cnt) {
  351. dev_warn(&dev->pdev->dev, "event on port %d\n", port);
  352. return;
  353. }
  354. pvrdma_dispatch_event(dev, port, type);
  355. }
  356. static inline struct pvrdma_eqe *get_eqe(struct pvrdma_dev *dev, unsigned int i)
  357. {
  358. return (struct pvrdma_eqe *)pvrdma_page_dir_get_ptr(
  359. &dev->async_pdir,
  360. PAGE_SIZE +
  361. sizeof(struct pvrdma_eqe) * i);
  362. }
  363. static irqreturn_t pvrdma_intr1_handler(int irq, void *dev_id)
  364. {
  365. struct pvrdma_dev *dev = dev_id;
  366. struct pvrdma_ring *ring = &dev->async_ring_state->rx;
  367. int ring_slots = (dev->dsr->async_ring_pages.num_pages - 1) *
  368. PAGE_SIZE / sizeof(struct pvrdma_eqe);
  369. unsigned int head;
  370. dev_dbg(&dev->pdev->dev, "interrupt 1 (async event) handler\n");
  371. /*
  372. * Don't process events until the IB device is registered. Otherwise
  373. * we'll try to ib_dispatch_event() on an invalid device.
  374. */
  375. if (!dev->ib_active)
  376. return IRQ_HANDLED;
  377. while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
  378. struct pvrdma_eqe *eqe;
  379. eqe = get_eqe(dev, head);
  380. switch (eqe->type) {
  381. case PVRDMA_EVENT_QP_FATAL:
  382. case PVRDMA_EVENT_QP_REQ_ERR:
  383. case PVRDMA_EVENT_QP_ACCESS_ERR:
  384. case PVRDMA_EVENT_COMM_EST:
  385. case PVRDMA_EVENT_SQ_DRAINED:
  386. case PVRDMA_EVENT_PATH_MIG:
  387. case PVRDMA_EVENT_PATH_MIG_ERR:
  388. case PVRDMA_EVENT_QP_LAST_WQE_REACHED:
  389. pvrdma_qp_event(dev, eqe->info, eqe->type);
  390. break;
  391. case PVRDMA_EVENT_CQ_ERR:
  392. pvrdma_cq_event(dev, eqe->info, eqe->type);
  393. break;
  394. case PVRDMA_EVENT_SRQ_ERR:
  395. case PVRDMA_EVENT_SRQ_LIMIT_REACHED:
  396. pvrdma_srq_event(dev, eqe->info, eqe->type);
  397. break;
  398. case PVRDMA_EVENT_PORT_ACTIVE:
  399. case PVRDMA_EVENT_PORT_ERR:
  400. case PVRDMA_EVENT_LID_CHANGE:
  401. case PVRDMA_EVENT_PKEY_CHANGE:
  402. case PVRDMA_EVENT_SM_CHANGE:
  403. case PVRDMA_EVENT_CLIENT_REREGISTER:
  404. case PVRDMA_EVENT_GID_CHANGE:
  405. pvrdma_dev_event(dev, eqe->info, eqe->type);
  406. break;
  407. case PVRDMA_EVENT_DEVICE_FATAL:
  408. pvrdma_dev_event(dev, 1, eqe->type);
  409. break;
  410. default:
  411. break;
  412. }
  413. pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
  414. }
  415. return IRQ_HANDLED;
  416. }
  417. static inline struct pvrdma_cqne *get_cqne(struct pvrdma_dev *dev,
  418. unsigned int i)
  419. {
  420. return (struct pvrdma_cqne *)pvrdma_page_dir_get_ptr(
  421. &dev->cq_pdir,
  422. PAGE_SIZE +
  423. sizeof(struct pvrdma_cqne) * i);
  424. }
  425. static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id)
  426. {
  427. struct pvrdma_dev *dev = dev_id;
  428. struct pvrdma_ring *ring = &dev->cq_ring_state->rx;
  429. int ring_slots = (dev->dsr->cq_ring_pages.num_pages - 1) * PAGE_SIZE /
  430. sizeof(struct pvrdma_cqne);
  431. unsigned int head;
  432. unsigned long flags;
  433. dev_dbg(&dev->pdev->dev, "interrupt x (completion) handler\n");
  434. while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
  435. struct pvrdma_cqne *cqne;
  436. struct pvrdma_cq *cq;
  437. cqne = get_cqne(dev, head);
  438. spin_lock_irqsave(&dev->cq_tbl_lock, flags);
  439. cq = dev->cq_tbl[cqne->info % dev->dsr->caps.max_cq];
  440. if (cq)
  441. refcount_inc(&cq->refcnt);
  442. spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
  443. if (cq && cq->ibcq.comp_handler)
  444. cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
  445. if (cq) {
  446. if (refcount_dec_and_test(&cq->refcnt))
  447. complete(&cq->free);
  448. }
  449. pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
  450. }
  451. return IRQ_HANDLED;
  452. }
  453. static void pvrdma_free_irq(struct pvrdma_dev *dev)
  454. {
  455. int i;
  456. dev_dbg(&dev->pdev->dev, "freeing interrupts\n");
  457. for (i = 0; i < dev->nr_vectors; i++)
  458. free_irq(pci_irq_vector(dev->pdev, i), dev);
  459. }
  460. static void pvrdma_enable_intrs(struct pvrdma_dev *dev)
  461. {
  462. dev_dbg(&dev->pdev->dev, "enable interrupts\n");
  463. pvrdma_write_reg(dev, PVRDMA_REG_IMR, 0);
  464. }
  465. static void pvrdma_disable_intrs(struct pvrdma_dev *dev)
  466. {
  467. dev_dbg(&dev->pdev->dev, "disable interrupts\n");
  468. pvrdma_write_reg(dev, PVRDMA_REG_IMR, ~0);
  469. }
  470. static int pvrdma_alloc_intrs(struct pvrdma_dev *dev)
  471. {
  472. struct pci_dev *pdev = dev->pdev;
  473. int ret = 0, i;
  474. ret = pci_alloc_irq_vectors(pdev, 1, PVRDMA_MAX_INTERRUPTS,
  475. PCI_IRQ_MSIX);
  476. if (ret < 0) {
  477. ret = pci_alloc_irq_vectors(pdev, 1, 1,
  478. PCI_IRQ_MSI | PCI_IRQ_LEGACY);
  479. if (ret < 0)
  480. return ret;
  481. }
  482. dev->nr_vectors = ret;
  483. ret = request_irq(pci_irq_vector(dev->pdev, 0), pvrdma_intr0_handler,
  484. pdev->msix_enabled ? 0 : IRQF_SHARED, DRV_NAME, dev);
  485. if (ret) {
  486. dev_err(&dev->pdev->dev,
  487. "failed to request interrupt 0\n");
  488. goto out_free_vectors;
  489. }
  490. for (i = 1; i < dev->nr_vectors; i++) {
  491. ret = request_irq(pci_irq_vector(dev->pdev, i),
  492. i == 1 ? pvrdma_intr1_handler :
  493. pvrdma_intrx_handler,
  494. 0, DRV_NAME, dev);
  495. if (ret) {
  496. dev_err(&dev->pdev->dev,
  497. "failed to request interrupt %d\n", i);
  498. goto free_irqs;
  499. }
  500. }
  501. return 0;
  502. free_irqs:
  503. while (--i >= 0)
  504. free_irq(pci_irq_vector(dev->pdev, i), dev);
  505. out_free_vectors:
  506. pci_free_irq_vectors(pdev);
  507. return ret;
  508. }
  509. static void pvrdma_free_slots(struct pvrdma_dev *dev)
  510. {
  511. struct pci_dev *pdev = dev->pdev;
  512. if (dev->resp_slot)
  513. dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->resp_slot,
  514. dev->dsr->resp_slot_dma);
  515. if (dev->cmd_slot)
  516. dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->cmd_slot,
  517. dev->dsr->cmd_slot_dma);
  518. }
  519. static int pvrdma_add_gid_at_index(struct pvrdma_dev *dev,
  520. const union ib_gid *gid,
  521. u8 gid_type,
  522. int index)
  523. {
  524. int ret;
  525. union pvrdma_cmd_req req;
  526. struct pvrdma_cmd_create_bind *cmd_bind = &req.create_bind;
  527. if (!dev->sgid_tbl) {
  528. dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
  529. return -EINVAL;
  530. }
  531. memset(cmd_bind, 0, sizeof(*cmd_bind));
  532. cmd_bind->hdr.cmd = PVRDMA_CMD_CREATE_BIND;
  533. memcpy(cmd_bind->new_gid, gid->raw, 16);
  534. cmd_bind->mtu = ib_mtu_enum_to_int(IB_MTU_1024);
  535. cmd_bind->vlan = 0xfff;
  536. cmd_bind->index = index;
  537. cmd_bind->gid_type = gid_type;
  538. ret = pvrdma_cmd_post(dev, &req, NULL, 0);
  539. if (ret < 0) {
  540. dev_warn(&dev->pdev->dev,
  541. "could not create binding, error: %d\n", ret);
  542. return -EFAULT;
  543. }
  544. memcpy(&dev->sgid_tbl[index], gid, sizeof(*gid));
  545. return 0;
  546. }
  547. static int pvrdma_add_gid(const struct ib_gid_attr *attr, void **context)
  548. {
  549. struct pvrdma_dev *dev = to_vdev(attr->device);
  550. return pvrdma_add_gid_at_index(dev, &attr->gid,
  551. ib_gid_type_to_pvrdma(attr->gid_type),
  552. attr->index);
  553. }
  554. static int pvrdma_del_gid_at_index(struct pvrdma_dev *dev, int index)
  555. {
  556. int ret;
  557. union pvrdma_cmd_req req;
  558. struct pvrdma_cmd_destroy_bind *cmd_dest = &req.destroy_bind;
  559. /* Update sgid table. */
  560. if (!dev->sgid_tbl) {
  561. dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
  562. return -EINVAL;
  563. }
  564. memset(cmd_dest, 0, sizeof(*cmd_dest));
  565. cmd_dest->hdr.cmd = PVRDMA_CMD_DESTROY_BIND;
  566. memcpy(cmd_dest->dest_gid, &dev->sgid_tbl[index], 16);
  567. cmd_dest->index = index;
  568. ret = pvrdma_cmd_post(dev, &req, NULL, 0);
  569. if (ret < 0) {
  570. dev_warn(&dev->pdev->dev,
  571. "could not destroy binding, error: %d\n", ret);
  572. return ret;
  573. }
  574. memset(&dev->sgid_tbl[index], 0, 16);
  575. return 0;
  576. }
  577. static int pvrdma_del_gid(const struct ib_gid_attr *attr, void **context)
  578. {
  579. struct pvrdma_dev *dev = to_vdev(attr->device);
  580. dev_dbg(&dev->pdev->dev, "removing gid at index %u from %s",
  581. attr->index, dev->netdev->name);
  582. return pvrdma_del_gid_at_index(dev, attr->index);
  583. }
  584. static void pvrdma_netdevice_event_handle(struct pvrdma_dev *dev,
  585. struct net_device *ndev,
  586. unsigned long event)
  587. {
  588. struct pci_dev *pdev_net;
  589. unsigned int slot;
  590. switch (event) {
  591. case NETDEV_REBOOT:
  592. case NETDEV_DOWN:
  593. pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
  594. break;
  595. case NETDEV_UP:
  596. pvrdma_write_reg(dev, PVRDMA_REG_CTL,
  597. PVRDMA_DEVICE_CTL_UNQUIESCE);
  598. mb();
  599. if (pvrdma_read_reg(dev, PVRDMA_REG_ERR))
  600. dev_err(&dev->pdev->dev,
  601. "failed to activate device during link up\n");
  602. else
  603. pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
  604. break;
  605. case NETDEV_UNREGISTER:
  606. dev_put(dev->netdev);
  607. dev->netdev = NULL;
  608. break;
  609. case NETDEV_REGISTER:
  610. /* vmxnet3 will have same bus, slot. But func will be 0 */
  611. slot = PCI_SLOT(dev->pdev->devfn);
  612. pdev_net = pci_get_slot(dev->pdev->bus,
  613. PCI_DEVFN(slot, 0));
  614. if ((dev->netdev == NULL) &&
  615. (pci_get_drvdata(pdev_net) == ndev)) {
  616. /* this is our netdev */
  617. dev->netdev = ndev;
  618. dev_hold(ndev);
  619. }
  620. pci_dev_put(pdev_net);
  621. break;
  622. default:
  623. dev_dbg(&dev->pdev->dev, "ignore netdevice event %ld on %s\n",
  624. event, dev_name(&dev->ib_dev.dev));
  625. break;
  626. }
  627. }
  628. static void pvrdma_netdevice_event_work(struct work_struct *work)
  629. {
  630. struct pvrdma_netdevice_work *netdev_work;
  631. struct pvrdma_dev *dev;
  632. netdev_work = container_of(work, struct pvrdma_netdevice_work, work);
  633. mutex_lock(&pvrdma_device_list_lock);
  634. list_for_each_entry(dev, &pvrdma_device_list, device_link) {
  635. if ((netdev_work->event == NETDEV_REGISTER) ||
  636. (dev->netdev == netdev_work->event_netdev)) {
  637. pvrdma_netdevice_event_handle(dev,
  638. netdev_work->event_netdev,
  639. netdev_work->event);
  640. break;
  641. }
  642. }
  643. mutex_unlock(&pvrdma_device_list_lock);
  644. kfree(netdev_work);
  645. }
  646. static int pvrdma_netdevice_event(struct notifier_block *this,
  647. unsigned long event, void *ptr)
  648. {
  649. struct net_device *event_netdev = netdev_notifier_info_to_dev(ptr);
  650. struct pvrdma_netdevice_work *netdev_work;
  651. netdev_work = kmalloc(sizeof(*netdev_work), GFP_ATOMIC);
  652. if (!netdev_work)
  653. return NOTIFY_BAD;
  654. INIT_WORK(&netdev_work->work, pvrdma_netdevice_event_work);
  655. netdev_work->event_netdev = event_netdev;
  656. netdev_work->event = event;
  657. queue_work(event_wq, &netdev_work->work);
  658. return NOTIFY_DONE;
  659. }
  660. static int pvrdma_pci_probe(struct pci_dev *pdev,
  661. const struct pci_device_id *id)
  662. {
  663. struct pci_dev *pdev_net;
  664. struct pvrdma_dev *dev;
  665. int ret;
  666. unsigned long start;
  667. unsigned long len;
  668. dma_addr_t slot_dma = 0;
  669. dev_dbg(&pdev->dev, "initializing driver %s\n", pci_name(pdev));
  670. /* Allocate zero-out device */
  671. dev = (struct pvrdma_dev *)ib_alloc_device(sizeof(*dev));
  672. if (!dev) {
  673. dev_err(&pdev->dev, "failed to allocate IB device\n");
  674. return -ENOMEM;
  675. }
  676. mutex_lock(&pvrdma_device_list_lock);
  677. list_add(&dev->device_link, &pvrdma_device_list);
  678. mutex_unlock(&pvrdma_device_list_lock);
  679. ret = pvrdma_init_device(dev);
  680. if (ret)
  681. goto err_free_device;
  682. dev->pdev = pdev;
  683. pci_set_drvdata(pdev, dev);
  684. ret = pci_enable_device(pdev);
  685. if (ret) {
  686. dev_err(&pdev->dev, "cannot enable PCI device\n");
  687. goto err_free_device;
  688. }
  689. dev_dbg(&pdev->dev, "PCI resource flags BAR0 %#lx\n",
  690. pci_resource_flags(pdev, 0));
  691. dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
  692. (unsigned long long)pci_resource_len(pdev, 0));
  693. dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
  694. (unsigned long long)pci_resource_start(pdev, 0));
  695. dev_dbg(&pdev->dev, "PCI resource flags BAR1 %#lx\n",
  696. pci_resource_flags(pdev, 1));
  697. dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
  698. (unsigned long long)pci_resource_len(pdev, 1));
  699. dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
  700. (unsigned long long)pci_resource_start(pdev, 1));
  701. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  702. !(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
  703. dev_err(&pdev->dev, "PCI BAR region not MMIO\n");
  704. ret = -ENOMEM;
  705. goto err_free_device;
  706. }
  707. ret = pci_request_regions(pdev, DRV_NAME);
  708. if (ret) {
  709. dev_err(&pdev->dev, "cannot request PCI resources\n");
  710. goto err_disable_pdev;
  711. }
  712. /* Enable 64-Bit DMA */
  713. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
  714. ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  715. if (ret != 0) {
  716. dev_err(&pdev->dev,
  717. "pci_set_consistent_dma_mask failed\n");
  718. goto err_free_resource;
  719. }
  720. } else {
  721. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  722. if (ret != 0) {
  723. dev_err(&pdev->dev,
  724. "pci_set_dma_mask failed\n");
  725. goto err_free_resource;
  726. }
  727. }
  728. pci_set_master(pdev);
  729. /* Map register space */
  730. start = pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
  731. len = pci_resource_len(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
  732. dev->regs = ioremap(start, len);
  733. if (!dev->regs) {
  734. dev_err(&pdev->dev, "register mapping failed\n");
  735. ret = -ENOMEM;
  736. goto err_free_resource;
  737. }
  738. /* Setup per-device UAR. */
  739. dev->driver_uar.index = 0;
  740. dev->driver_uar.pfn =
  741. pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_UAR) >>
  742. PAGE_SHIFT;
  743. dev->driver_uar.map =
  744. ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  745. if (!dev->driver_uar.map) {
  746. dev_err(&pdev->dev, "failed to remap UAR pages\n");
  747. ret = -ENOMEM;
  748. goto err_unmap_regs;
  749. }
  750. dev->dsr_version = pvrdma_read_reg(dev, PVRDMA_REG_VERSION);
  751. dev_info(&pdev->dev, "device version %d, driver version %d\n",
  752. dev->dsr_version, PVRDMA_VERSION);
  753. dev->dsr = dma_zalloc_coherent(&pdev->dev, sizeof(*dev->dsr),
  754. &dev->dsrbase, GFP_KERNEL);
  755. if (!dev->dsr) {
  756. dev_err(&pdev->dev, "failed to allocate shared region\n");
  757. ret = -ENOMEM;
  758. goto err_uar_unmap;
  759. }
  760. /* Setup the shared region */
  761. dev->dsr->driver_version = PVRDMA_VERSION;
  762. dev->dsr->gos_info.gos_bits = sizeof(void *) == 4 ?
  763. PVRDMA_GOS_BITS_32 :
  764. PVRDMA_GOS_BITS_64;
  765. dev->dsr->gos_info.gos_type = PVRDMA_GOS_TYPE_LINUX;
  766. dev->dsr->gos_info.gos_ver = 1;
  767. dev->dsr->uar_pfn = dev->driver_uar.pfn;
  768. /* Command slot. */
  769. dev->cmd_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
  770. &slot_dma, GFP_KERNEL);
  771. if (!dev->cmd_slot) {
  772. ret = -ENOMEM;
  773. goto err_free_dsr;
  774. }
  775. dev->dsr->cmd_slot_dma = (u64)slot_dma;
  776. /* Response slot. */
  777. dev->resp_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
  778. &slot_dma, GFP_KERNEL);
  779. if (!dev->resp_slot) {
  780. ret = -ENOMEM;
  781. goto err_free_slots;
  782. }
  783. dev->dsr->resp_slot_dma = (u64)slot_dma;
  784. /* Async event ring */
  785. dev->dsr->async_ring_pages.num_pages = PVRDMA_NUM_RING_PAGES;
  786. ret = pvrdma_page_dir_init(dev, &dev->async_pdir,
  787. dev->dsr->async_ring_pages.num_pages, true);
  788. if (ret)
  789. goto err_free_slots;
  790. dev->async_ring_state = dev->async_pdir.pages[0];
  791. dev->dsr->async_ring_pages.pdir_dma = dev->async_pdir.dir_dma;
  792. /* CQ notification ring */
  793. dev->dsr->cq_ring_pages.num_pages = PVRDMA_NUM_RING_PAGES;
  794. ret = pvrdma_page_dir_init(dev, &dev->cq_pdir,
  795. dev->dsr->cq_ring_pages.num_pages, true);
  796. if (ret)
  797. goto err_free_async_ring;
  798. dev->cq_ring_state = dev->cq_pdir.pages[0];
  799. dev->dsr->cq_ring_pages.pdir_dma = dev->cq_pdir.dir_dma;
  800. /*
  801. * Write the PA of the shared region to the device. The writes must be
  802. * ordered such that the high bits are written last. When the writes
  803. * complete, the device will have filled out the capabilities.
  804. */
  805. pvrdma_write_reg(dev, PVRDMA_REG_DSRLOW, (u32)dev->dsrbase);
  806. pvrdma_write_reg(dev, PVRDMA_REG_DSRHIGH,
  807. (u32)((u64)(dev->dsrbase) >> 32));
  808. /* Make sure the write is complete before reading status. */
  809. mb();
  810. /* The driver supports RoCE V1 and V2. */
  811. if (!PVRDMA_SUPPORTED(dev)) {
  812. dev_err(&pdev->dev, "driver needs RoCE v1 or v2 support\n");
  813. ret = -EFAULT;
  814. goto err_free_cq_ring;
  815. }
  816. /* Paired vmxnet3 will have same bus, slot. But func will be 0 */
  817. pdev_net = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
  818. if (!pdev_net) {
  819. dev_err(&pdev->dev, "failed to find paired net device\n");
  820. ret = -ENODEV;
  821. goto err_free_cq_ring;
  822. }
  823. if (pdev_net->vendor != PCI_VENDOR_ID_VMWARE ||
  824. pdev_net->device != PCI_DEVICE_ID_VMWARE_VMXNET3) {
  825. dev_err(&pdev->dev, "failed to find paired vmxnet3 device\n");
  826. pci_dev_put(pdev_net);
  827. ret = -ENODEV;
  828. goto err_free_cq_ring;
  829. }
  830. dev->netdev = pci_get_drvdata(pdev_net);
  831. pci_dev_put(pdev_net);
  832. if (!dev->netdev) {
  833. dev_err(&pdev->dev, "failed to get vmxnet3 device\n");
  834. ret = -ENODEV;
  835. goto err_free_cq_ring;
  836. }
  837. dev_hold(dev->netdev);
  838. dev_info(&pdev->dev, "paired device to %s\n", dev->netdev->name);
  839. /* Interrupt setup */
  840. ret = pvrdma_alloc_intrs(dev);
  841. if (ret) {
  842. dev_err(&pdev->dev, "failed to allocate interrupts\n");
  843. ret = -ENOMEM;
  844. goto err_free_cq_ring;
  845. }
  846. /* Allocate UAR table. */
  847. ret = pvrdma_uar_table_init(dev);
  848. if (ret) {
  849. dev_err(&pdev->dev, "failed to allocate UAR table\n");
  850. ret = -ENOMEM;
  851. goto err_free_intrs;
  852. }
  853. /* Allocate GID table */
  854. dev->sgid_tbl = kcalloc(dev->dsr->caps.gid_tbl_len,
  855. sizeof(union ib_gid), GFP_KERNEL);
  856. if (!dev->sgid_tbl) {
  857. ret = -ENOMEM;
  858. goto err_free_uar_table;
  859. }
  860. dev_dbg(&pdev->dev, "gid table len %d\n", dev->dsr->caps.gid_tbl_len);
  861. pvrdma_enable_intrs(dev);
  862. /* Activate pvrdma device */
  863. pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_ACTIVATE);
  864. /* Make sure the write is complete before reading status. */
  865. mb();
  866. /* Check if device was successfully activated */
  867. ret = pvrdma_read_reg(dev, PVRDMA_REG_ERR);
  868. if (ret != 0) {
  869. dev_err(&pdev->dev, "failed to activate device\n");
  870. ret = -EFAULT;
  871. goto err_disable_intr;
  872. }
  873. /* Register IB device */
  874. ret = pvrdma_register_device(dev);
  875. if (ret) {
  876. dev_err(&pdev->dev, "failed to register IB device\n");
  877. goto err_disable_intr;
  878. }
  879. dev->nb_netdev.notifier_call = pvrdma_netdevice_event;
  880. ret = register_netdevice_notifier(&dev->nb_netdev);
  881. if (ret) {
  882. dev_err(&pdev->dev, "failed to register netdevice events\n");
  883. goto err_unreg_ibdev;
  884. }
  885. dev_info(&pdev->dev, "attached to device\n");
  886. return 0;
  887. err_unreg_ibdev:
  888. ib_unregister_device(&dev->ib_dev);
  889. err_disable_intr:
  890. pvrdma_disable_intrs(dev);
  891. kfree(dev->sgid_tbl);
  892. err_free_uar_table:
  893. pvrdma_uar_table_cleanup(dev);
  894. err_free_intrs:
  895. pvrdma_free_irq(dev);
  896. pci_free_irq_vectors(pdev);
  897. err_free_cq_ring:
  898. if (dev->netdev) {
  899. dev_put(dev->netdev);
  900. dev->netdev = NULL;
  901. }
  902. pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
  903. err_free_async_ring:
  904. pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
  905. err_free_slots:
  906. pvrdma_free_slots(dev);
  907. err_free_dsr:
  908. dma_free_coherent(&pdev->dev, sizeof(*dev->dsr), dev->dsr,
  909. dev->dsrbase);
  910. err_uar_unmap:
  911. iounmap(dev->driver_uar.map);
  912. err_unmap_regs:
  913. iounmap(dev->regs);
  914. err_free_resource:
  915. pci_release_regions(pdev);
  916. err_disable_pdev:
  917. pci_disable_device(pdev);
  918. pci_set_drvdata(pdev, NULL);
  919. err_free_device:
  920. mutex_lock(&pvrdma_device_list_lock);
  921. list_del(&dev->device_link);
  922. mutex_unlock(&pvrdma_device_list_lock);
  923. ib_dealloc_device(&dev->ib_dev);
  924. return ret;
  925. }
  926. static void pvrdma_pci_remove(struct pci_dev *pdev)
  927. {
  928. struct pvrdma_dev *dev = pci_get_drvdata(pdev);
  929. if (!dev)
  930. return;
  931. dev_info(&pdev->dev, "detaching from device\n");
  932. unregister_netdevice_notifier(&dev->nb_netdev);
  933. dev->nb_netdev.notifier_call = NULL;
  934. flush_workqueue(event_wq);
  935. if (dev->netdev) {
  936. dev_put(dev->netdev);
  937. dev->netdev = NULL;
  938. }
  939. /* Unregister ib device */
  940. ib_unregister_device(&dev->ib_dev);
  941. mutex_lock(&pvrdma_device_list_lock);
  942. list_del(&dev->device_link);
  943. mutex_unlock(&pvrdma_device_list_lock);
  944. pvrdma_disable_intrs(dev);
  945. pvrdma_free_irq(dev);
  946. pci_free_irq_vectors(pdev);
  947. /* Deactivate pvrdma device */
  948. pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_RESET);
  949. pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
  950. pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
  951. pvrdma_free_slots(dev);
  952. iounmap(dev->regs);
  953. kfree(dev->sgid_tbl);
  954. kfree(dev->cq_tbl);
  955. kfree(dev->srq_tbl);
  956. kfree(dev->qp_tbl);
  957. pvrdma_uar_table_cleanup(dev);
  958. iounmap(dev->driver_uar.map);
  959. ib_dealloc_device(&dev->ib_dev);
  960. /* Free pci resources */
  961. pci_release_regions(pdev);
  962. pci_disable_device(pdev);
  963. pci_set_drvdata(pdev, NULL);
  964. }
  965. static const struct pci_device_id pvrdma_pci_table[] = {
  966. { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, PCI_DEVICE_ID_VMWARE_PVRDMA), },
  967. { 0 },
  968. };
  969. MODULE_DEVICE_TABLE(pci, pvrdma_pci_table);
  970. static struct pci_driver pvrdma_driver = {
  971. .name = DRV_NAME,
  972. .id_table = pvrdma_pci_table,
  973. .probe = pvrdma_pci_probe,
  974. .remove = pvrdma_pci_remove,
  975. };
  976. static int __init pvrdma_init(void)
  977. {
  978. int err;
  979. event_wq = alloc_ordered_workqueue("pvrdma_event_wq", WQ_MEM_RECLAIM);
  980. if (!event_wq)
  981. return -ENOMEM;
  982. err = pci_register_driver(&pvrdma_driver);
  983. if (err)
  984. destroy_workqueue(event_wq);
  985. return err;
  986. }
  987. static void __exit pvrdma_cleanup(void)
  988. {
  989. pci_unregister_driver(&pvrdma_driver);
  990. destroy_workqueue(event_wq);
  991. }
  992. module_init(pvrdma_init);
  993. module_exit(pvrdma_cleanup);
  994. MODULE_AUTHOR("VMware, Inc");
  995. MODULE_DESCRIPTION("VMware Paravirtual RDMA driver");
  996. MODULE_LICENSE("Dual BSD/GPL");