hns_roce_main.c 23 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/acpi.h>
  34. #include <linux/of_platform.h>
  35. #include <linux/module.h>
  36. #include <rdma/ib_addr.h>
  37. #include <rdma/ib_smi.h>
  38. #include <rdma/ib_user_verbs.h>
  39. #include <rdma/ib_cache.h>
  40. #include "hns_roce_common.h"
  41. #include "hns_roce_device.h"
  42. #include <rdma/hns-abi.h>
  43. #include "hns_roce_hem.h"
  44. /**
  45. * hns_get_gid_index - Get gid index.
  46. * @hr_dev: pointer to structure hns_roce_dev.
  47. * @port: port, value range: 0 ~ MAX
  48. * @gid_index: gid_index, value range: 0 ~ MAX
  49. * Description:
  50. * N ports shared gids, allocation method as follow:
  51. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  52. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  53. * And so on
  54. */
  55. int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
  56. {
  57. return gid_index * hr_dev->caps.num_ports + port;
  58. }
  59. EXPORT_SYMBOL_GPL(hns_get_gid_index);
  60. static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
  61. {
  62. u8 phy_port;
  63. u32 i = 0;
  64. if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
  65. return 0;
  66. for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
  67. hr_dev->dev_addr[port][i] = addr[i];
  68. phy_port = hr_dev->iboe.phy_port[port];
  69. return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  70. }
  71. static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
  72. {
  73. struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  74. u8 port = attr->port_num - 1;
  75. unsigned long flags;
  76. int ret;
  77. if (port >= hr_dev->caps.num_ports)
  78. return -EINVAL;
  79. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  80. ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
  81. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  82. return ret;
  83. }
  84. static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
  85. {
  86. struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  87. struct ib_gid_attr zattr = { };
  88. u8 port = attr->port_num - 1;
  89. unsigned long flags;
  90. int ret;
  91. if (port >= hr_dev->caps.num_ports)
  92. return -EINVAL;
  93. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  94. ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
  95. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  96. return ret;
  97. }
  98. static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
  99. unsigned long event)
  100. {
  101. struct device *dev = hr_dev->dev;
  102. struct net_device *netdev;
  103. int ret = 0;
  104. netdev = hr_dev->iboe.netdevs[port];
  105. if (!netdev) {
  106. dev_err(dev, "port(%d) can't find netdev\n", port);
  107. return -ENODEV;
  108. }
  109. switch (event) {
  110. case NETDEV_UP:
  111. case NETDEV_CHANGE:
  112. case NETDEV_REGISTER:
  113. case NETDEV_CHANGEADDR:
  114. ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
  115. break;
  116. case NETDEV_DOWN:
  117. /*
  118. * In v1 engine, only support all ports closed together.
  119. */
  120. break;
  121. default:
  122. dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
  123. break;
  124. }
  125. return ret;
  126. }
  127. static int hns_roce_netdev_event(struct notifier_block *self,
  128. unsigned long event, void *ptr)
  129. {
  130. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  131. struct hns_roce_ib_iboe *iboe = NULL;
  132. struct hns_roce_dev *hr_dev = NULL;
  133. u8 port = 0;
  134. int ret = 0;
  135. hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
  136. iboe = &hr_dev->iboe;
  137. for (port = 0; port < hr_dev->caps.num_ports; port++) {
  138. if (dev == iboe->netdevs[port]) {
  139. ret = handle_en_event(hr_dev, port, event);
  140. if (ret)
  141. return NOTIFY_DONE;
  142. break;
  143. }
  144. }
  145. return NOTIFY_DONE;
  146. }
  147. static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
  148. {
  149. int ret;
  150. u8 i;
  151. for (i = 0; i < hr_dev->caps.num_ports; i++) {
  152. if (hr_dev->hw->set_mtu)
  153. hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
  154. hr_dev->caps.max_mtu);
  155. ret = hns_roce_set_mac(hr_dev, i,
  156. hr_dev->iboe.netdevs[i]->dev_addr);
  157. if (ret)
  158. return ret;
  159. }
  160. return 0;
  161. }
  162. static int hns_roce_query_device(struct ib_device *ib_dev,
  163. struct ib_device_attr *props,
  164. struct ib_udata *uhw)
  165. {
  166. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  167. memset(props, 0, sizeof(*props));
  168. props->fw_ver = hr_dev->caps.fw_ver;
  169. props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
  170. props->max_mr_size = (u64)(~(0ULL));
  171. props->page_size_cap = hr_dev->caps.page_size_cap;
  172. props->vendor_id = hr_dev->vendor_id;
  173. props->vendor_part_id = hr_dev->vendor_part_id;
  174. props->hw_ver = hr_dev->hw_rev;
  175. props->max_qp = hr_dev->caps.num_qps;
  176. props->max_qp_wr = hr_dev->caps.max_wqes;
  177. props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
  178. IB_DEVICE_RC_RNR_NAK_GEN;
  179. props->max_send_sge = hr_dev->caps.max_sq_sg;
  180. props->max_recv_sge = hr_dev->caps.max_rq_sg;
  181. props->max_sge_rd = 1;
  182. props->max_cq = hr_dev->caps.num_cqs;
  183. props->max_cqe = hr_dev->caps.max_cqes;
  184. props->max_mr = hr_dev->caps.num_mtpts;
  185. props->max_pd = hr_dev->caps.num_pds;
  186. props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
  187. props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
  188. props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
  189. IB_ATOMIC_HCA : IB_ATOMIC_NONE;
  190. props->max_pkeys = 1;
  191. props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
  192. return 0;
  193. }
  194. static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
  195. u8 port_num)
  196. {
  197. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  198. struct net_device *ndev;
  199. if (port_num < 1 || port_num > hr_dev->caps.num_ports)
  200. return NULL;
  201. rcu_read_lock();
  202. ndev = hr_dev->iboe.netdevs[port_num - 1];
  203. if (ndev)
  204. dev_hold(ndev);
  205. rcu_read_unlock();
  206. return ndev;
  207. }
  208. static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
  209. struct ib_port_attr *props)
  210. {
  211. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  212. struct device *dev = hr_dev->dev;
  213. struct net_device *net_dev;
  214. unsigned long flags;
  215. enum ib_mtu mtu;
  216. u8 port;
  217. assert(port_num > 0);
  218. port = port_num - 1;
  219. /* props being zeroed by the caller, avoid zeroing it here */
  220. props->max_mtu = hr_dev->caps.max_mtu;
  221. props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
  222. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  223. IB_PORT_VENDOR_CLASS_SUP |
  224. IB_PORT_BOOT_MGMT_SUP;
  225. props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
  226. props->pkey_tbl_len = 1;
  227. props->active_width = IB_WIDTH_4X;
  228. props->active_speed = 1;
  229. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  230. net_dev = hr_dev->iboe.netdevs[port];
  231. if (!net_dev) {
  232. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  233. dev_err(dev, "find netdev %d failed!\r\n", port);
  234. return -EINVAL;
  235. }
  236. mtu = iboe_get_mtu(net_dev->mtu);
  237. props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
  238. props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
  239. IB_PORT_ACTIVE : IB_PORT_DOWN;
  240. props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
  241. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  242. return 0;
  243. }
  244. static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
  245. u8 port_num)
  246. {
  247. return IB_LINK_LAYER_ETHERNET;
  248. }
  249. static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
  250. u16 *pkey)
  251. {
  252. *pkey = PKEY_ID;
  253. return 0;
  254. }
  255. static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
  256. struct ib_device_modify *props)
  257. {
  258. unsigned long flags;
  259. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  260. return -EOPNOTSUPP;
  261. if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
  262. spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
  263. memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
  264. spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
  265. }
  266. return 0;
  267. }
  268. static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
  269. struct ib_port_modify *props)
  270. {
  271. return 0;
  272. }
  273. static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
  274. struct ib_udata *udata)
  275. {
  276. int ret = 0;
  277. struct hns_roce_ucontext *context;
  278. struct hns_roce_ib_alloc_ucontext_resp resp = {};
  279. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  280. if (!hr_dev->active)
  281. return ERR_PTR(-EAGAIN);
  282. resp.qp_tab_size = hr_dev->caps.num_qps;
  283. context = kmalloc(sizeof(*context), GFP_KERNEL);
  284. if (!context)
  285. return ERR_PTR(-ENOMEM);
  286. ret = hns_roce_uar_alloc(hr_dev, &context->uar);
  287. if (ret)
  288. goto error_fail_uar_alloc;
  289. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
  290. INIT_LIST_HEAD(&context->page_list);
  291. mutex_init(&context->page_mutex);
  292. }
  293. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  294. if (ret)
  295. goto error_fail_copy_to_udata;
  296. return &context->ibucontext;
  297. error_fail_copy_to_udata:
  298. hns_roce_uar_free(hr_dev, &context->uar);
  299. error_fail_uar_alloc:
  300. kfree(context);
  301. return ERR_PTR(ret);
  302. }
  303. static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
  304. {
  305. struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
  306. hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
  307. kfree(context);
  308. return 0;
  309. }
  310. static int hns_roce_mmap(struct ib_ucontext *context,
  311. struct vm_area_struct *vma)
  312. {
  313. struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
  314. switch (vma->vm_pgoff) {
  315. case 0:
  316. return rdma_user_mmap_io(context, vma,
  317. to_hr_ucontext(context)->uar.pfn,
  318. PAGE_SIZE,
  319. pgprot_noncached(vma->vm_page_prot));
  320. /* vm_pgoff: 1 -- TPTR */
  321. case 1:
  322. if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size)
  323. return -EINVAL;
  324. /*
  325. * FIXME: using io_remap_pfn_range on the dma address returned
  326. * by dma_alloc_coherent is totally wrong.
  327. */
  328. return rdma_user_mmap_io(context, vma,
  329. hr_dev->tptr_dma_addr >> PAGE_SHIFT,
  330. hr_dev->tptr_size,
  331. vma->vm_page_prot);
  332. default:
  333. return -EINVAL;
  334. }
  335. }
  336. static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
  337. struct ib_port_immutable *immutable)
  338. {
  339. struct ib_port_attr attr;
  340. int ret;
  341. ret = ib_query_port(ib_dev, port_num, &attr);
  342. if (ret)
  343. return ret;
  344. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  345. immutable->gid_tbl_len = attr.gid_tbl_len;
  346. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  347. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  348. if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
  349. immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  350. return 0;
  351. }
  352. static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
  353. {
  354. }
  355. static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
  356. {
  357. struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
  358. hr_dev->active = false;
  359. unregister_netdevice_notifier(&iboe->nb);
  360. ib_unregister_device(&hr_dev->ib_dev);
  361. }
  362. static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
  363. {
  364. int ret;
  365. struct hns_roce_ib_iboe *iboe = NULL;
  366. struct ib_device *ib_dev = NULL;
  367. struct device *dev = hr_dev->dev;
  368. iboe = &hr_dev->iboe;
  369. spin_lock_init(&iboe->lock);
  370. ib_dev = &hr_dev->ib_dev;
  371. ib_dev->owner = THIS_MODULE;
  372. ib_dev->node_type = RDMA_NODE_IB_CA;
  373. ib_dev->dev.parent = dev;
  374. ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
  375. ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
  376. ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
  377. ib_dev->uverbs_abi_ver = 1;
  378. ib_dev->uverbs_cmd_mask =
  379. (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
  380. (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  381. (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
  382. (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
  383. (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
  384. (1ULL << IB_USER_VERBS_CMD_REG_MR) |
  385. (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
  386. (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  387. (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
  388. (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
  389. (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
  390. (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
  391. (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
  392. (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
  393. ib_dev->uverbs_ex_cmd_mask |=
  394. (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
  395. /* HCA||device||port */
  396. ib_dev->modify_device = hns_roce_modify_device;
  397. ib_dev->query_device = hns_roce_query_device;
  398. ib_dev->query_port = hns_roce_query_port;
  399. ib_dev->modify_port = hns_roce_modify_port;
  400. ib_dev->get_link_layer = hns_roce_get_link_layer;
  401. ib_dev->get_netdev = hns_roce_get_netdev;
  402. ib_dev->add_gid = hns_roce_add_gid;
  403. ib_dev->del_gid = hns_roce_del_gid;
  404. ib_dev->query_pkey = hns_roce_query_pkey;
  405. ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
  406. ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
  407. ib_dev->mmap = hns_roce_mmap;
  408. /* PD */
  409. ib_dev->alloc_pd = hns_roce_alloc_pd;
  410. ib_dev->dealloc_pd = hns_roce_dealloc_pd;
  411. /* AH */
  412. ib_dev->create_ah = hns_roce_create_ah;
  413. ib_dev->query_ah = hns_roce_query_ah;
  414. ib_dev->destroy_ah = hns_roce_destroy_ah;
  415. /* QP */
  416. ib_dev->create_qp = hns_roce_create_qp;
  417. ib_dev->modify_qp = hns_roce_modify_qp;
  418. ib_dev->query_qp = hr_dev->hw->query_qp;
  419. ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
  420. ib_dev->post_send = hr_dev->hw->post_send;
  421. ib_dev->post_recv = hr_dev->hw->post_recv;
  422. /* CQ */
  423. ib_dev->create_cq = hns_roce_ib_create_cq;
  424. ib_dev->modify_cq = hr_dev->hw->modify_cq;
  425. ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
  426. ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
  427. ib_dev->poll_cq = hr_dev->hw->poll_cq;
  428. /* MR */
  429. ib_dev->get_dma_mr = hns_roce_get_dma_mr;
  430. ib_dev->reg_user_mr = hns_roce_reg_user_mr;
  431. ib_dev->dereg_mr = hns_roce_dereg_mr;
  432. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
  433. ib_dev->rereg_user_mr = hns_roce_rereg_user_mr;
  434. ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
  435. }
  436. /* MW */
  437. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) {
  438. ib_dev->alloc_mw = hns_roce_alloc_mw;
  439. ib_dev->dealloc_mw = hns_roce_dealloc_mw;
  440. ib_dev->uverbs_cmd_mask |=
  441. (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) |
  442. (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW);
  443. }
  444. /* FRMR */
  445. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) {
  446. ib_dev->alloc_mr = hns_roce_alloc_mr;
  447. ib_dev->map_mr_sg = hns_roce_map_mr_sg;
  448. }
  449. /* OTHERS */
  450. ib_dev->get_port_immutable = hns_roce_port_immutable;
  451. ib_dev->disassociate_ucontext = hns_roce_disassociate_ucontext;
  452. ib_dev->driver_id = RDMA_DRIVER_HNS;
  453. ret = ib_register_device(ib_dev, "hns_%d", NULL);
  454. if (ret) {
  455. dev_err(dev, "ib_register_device failed!\n");
  456. return ret;
  457. }
  458. ret = hns_roce_setup_mtu_mac(hr_dev);
  459. if (ret) {
  460. dev_err(dev, "setup_mtu_mac failed!\n");
  461. goto error_failed_setup_mtu_mac;
  462. }
  463. iboe->nb.notifier_call = hns_roce_netdev_event;
  464. ret = register_netdevice_notifier(&iboe->nb);
  465. if (ret) {
  466. dev_err(dev, "register_netdevice_notifier failed!\n");
  467. goto error_failed_setup_mtu_mac;
  468. }
  469. hr_dev->active = true;
  470. return 0;
  471. error_failed_setup_mtu_mac:
  472. ib_unregister_device(ib_dev);
  473. return ret;
  474. }
  475. static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
  476. {
  477. int ret;
  478. struct device *dev = hr_dev->dev;
  479. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
  480. HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
  481. hr_dev->caps.num_mtt_segs, 1);
  482. if (ret) {
  483. dev_err(dev, "Failed to init MTT context memory, aborting.\n");
  484. return ret;
  485. }
  486. if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
  487. ret = hns_roce_init_hem_table(hr_dev,
  488. &hr_dev->mr_table.mtt_cqe_table,
  489. HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
  490. hr_dev->caps.num_cqe_segs, 1);
  491. if (ret) {
  492. dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
  493. goto err_unmap_cqe;
  494. }
  495. }
  496. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
  497. HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
  498. hr_dev->caps.num_mtpts, 1);
  499. if (ret) {
  500. dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
  501. goto err_unmap_mtt;
  502. }
  503. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
  504. HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
  505. hr_dev->caps.num_qps, 1);
  506. if (ret) {
  507. dev_err(dev, "Failed to init QP context memory, aborting.\n");
  508. goto err_unmap_dmpt;
  509. }
  510. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
  511. HEM_TYPE_IRRL,
  512. hr_dev->caps.irrl_entry_sz *
  513. hr_dev->caps.max_qp_init_rdma,
  514. hr_dev->caps.num_qps, 1);
  515. if (ret) {
  516. dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
  517. goto err_unmap_qp;
  518. }
  519. if (hr_dev->caps.trrl_entry_sz) {
  520. ret = hns_roce_init_hem_table(hr_dev,
  521. &hr_dev->qp_table.trrl_table,
  522. HEM_TYPE_TRRL,
  523. hr_dev->caps.trrl_entry_sz *
  524. hr_dev->caps.max_qp_dest_rdma,
  525. hr_dev->caps.num_qps, 1);
  526. if (ret) {
  527. dev_err(dev,
  528. "Failed to init trrl_table memory, aborting.\n");
  529. goto err_unmap_irrl;
  530. }
  531. }
  532. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
  533. HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
  534. hr_dev->caps.num_cqs, 1);
  535. if (ret) {
  536. dev_err(dev, "Failed to init CQ context memory, aborting.\n");
  537. goto err_unmap_trrl;
  538. }
  539. return 0;
  540. err_unmap_trrl:
  541. if (hr_dev->caps.trrl_entry_sz)
  542. hns_roce_cleanup_hem_table(hr_dev,
  543. &hr_dev->qp_table.trrl_table);
  544. err_unmap_irrl:
  545. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
  546. err_unmap_qp:
  547. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
  548. err_unmap_dmpt:
  549. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
  550. err_unmap_mtt:
  551. if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
  552. hns_roce_cleanup_hem_table(hr_dev,
  553. &hr_dev->mr_table.mtt_cqe_table);
  554. err_unmap_cqe:
  555. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
  556. return ret;
  557. }
  558. /**
  559. * hns_roce_setup_hca - setup host channel adapter
  560. * @hr_dev: pointer to hns roce device
  561. * Return : int
  562. */
  563. static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
  564. {
  565. int ret;
  566. struct device *dev = hr_dev->dev;
  567. spin_lock_init(&hr_dev->sm_lock);
  568. spin_lock_init(&hr_dev->bt_cmd_lock);
  569. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
  570. INIT_LIST_HEAD(&hr_dev->pgdir_list);
  571. mutex_init(&hr_dev->pgdir_mutex);
  572. }
  573. ret = hns_roce_init_uar_table(hr_dev);
  574. if (ret) {
  575. dev_err(dev, "Failed to initialize uar table. aborting\n");
  576. return ret;
  577. }
  578. ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
  579. if (ret) {
  580. dev_err(dev, "Failed to allocate priv_uar.\n");
  581. goto err_uar_table_free;
  582. }
  583. ret = hns_roce_init_pd_table(hr_dev);
  584. if (ret) {
  585. dev_err(dev, "Failed to init protected domain table.\n");
  586. goto err_uar_alloc_free;
  587. }
  588. ret = hns_roce_init_mr_table(hr_dev);
  589. if (ret) {
  590. dev_err(dev, "Failed to init memory region table.\n");
  591. goto err_pd_table_free;
  592. }
  593. ret = hns_roce_init_cq_table(hr_dev);
  594. if (ret) {
  595. dev_err(dev, "Failed to init completion queue table.\n");
  596. goto err_mr_table_free;
  597. }
  598. ret = hns_roce_init_qp_table(hr_dev);
  599. if (ret) {
  600. dev_err(dev, "Failed to init queue pair table.\n");
  601. goto err_cq_table_free;
  602. }
  603. return 0;
  604. err_cq_table_free:
  605. hns_roce_cleanup_cq_table(hr_dev);
  606. err_mr_table_free:
  607. hns_roce_cleanup_mr_table(hr_dev);
  608. err_pd_table_free:
  609. hns_roce_cleanup_pd_table(hr_dev);
  610. err_uar_alloc_free:
  611. hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
  612. err_uar_table_free:
  613. hns_roce_cleanup_uar_table(hr_dev);
  614. return ret;
  615. }
  616. int hns_roce_init(struct hns_roce_dev *hr_dev)
  617. {
  618. int ret;
  619. struct device *dev = hr_dev->dev;
  620. if (hr_dev->hw->reset) {
  621. ret = hr_dev->hw->reset(hr_dev, true);
  622. if (ret) {
  623. dev_err(dev, "Reset RoCE engine failed!\n");
  624. return ret;
  625. }
  626. }
  627. hr_dev->is_reset = false;
  628. if (hr_dev->hw->cmq_init) {
  629. ret = hr_dev->hw->cmq_init(hr_dev);
  630. if (ret) {
  631. dev_err(dev, "Init RoCE Command Queue failed!\n");
  632. goto error_failed_cmq_init;
  633. }
  634. }
  635. ret = hr_dev->hw->hw_profile(hr_dev);
  636. if (ret) {
  637. dev_err(dev, "Get RoCE engine profile failed!\n");
  638. goto error_failed_cmd_init;
  639. }
  640. ret = hns_roce_cmd_init(hr_dev);
  641. if (ret) {
  642. dev_err(dev, "cmd init failed!\n");
  643. goto error_failed_cmd_init;
  644. }
  645. ret = hr_dev->hw->init_eq(hr_dev);
  646. if (ret) {
  647. dev_err(dev, "eq init failed!\n");
  648. goto error_failed_eq_table;
  649. }
  650. if (hr_dev->cmd_mod) {
  651. ret = hns_roce_cmd_use_events(hr_dev);
  652. if (ret) {
  653. dev_err(dev, "Switch to event-driven cmd failed!\n");
  654. goto error_failed_use_event;
  655. }
  656. }
  657. ret = hns_roce_init_hem(hr_dev);
  658. if (ret) {
  659. dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
  660. goto error_failed_init_hem;
  661. }
  662. ret = hns_roce_setup_hca(hr_dev);
  663. if (ret) {
  664. dev_err(dev, "setup hca failed!\n");
  665. goto error_failed_setup_hca;
  666. }
  667. if (hr_dev->hw->hw_init) {
  668. ret = hr_dev->hw->hw_init(hr_dev);
  669. if (ret) {
  670. dev_err(dev, "hw_init failed!\n");
  671. goto error_failed_engine_init;
  672. }
  673. }
  674. ret = hns_roce_register_device(hr_dev);
  675. if (ret)
  676. goto error_failed_register_device;
  677. return 0;
  678. error_failed_register_device:
  679. if (hr_dev->hw->hw_exit)
  680. hr_dev->hw->hw_exit(hr_dev);
  681. error_failed_engine_init:
  682. hns_roce_cleanup_bitmap(hr_dev);
  683. error_failed_setup_hca:
  684. hns_roce_cleanup_hem(hr_dev);
  685. error_failed_init_hem:
  686. if (hr_dev->cmd_mod)
  687. hns_roce_cmd_use_polling(hr_dev);
  688. error_failed_use_event:
  689. hr_dev->hw->cleanup_eq(hr_dev);
  690. error_failed_eq_table:
  691. hns_roce_cmd_cleanup(hr_dev);
  692. error_failed_cmd_init:
  693. if (hr_dev->hw->cmq_exit)
  694. hr_dev->hw->cmq_exit(hr_dev);
  695. error_failed_cmq_init:
  696. if (hr_dev->hw->reset) {
  697. if (hr_dev->hw->reset(hr_dev, false))
  698. dev_err(dev, "Dereset RoCE engine failed!\n");
  699. }
  700. return ret;
  701. }
  702. EXPORT_SYMBOL_GPL(hns_roce_init);
  703. void hns_roce_exit(struct hns_roce_dev *hr_dev)
  704. {
  705. hns_roce_unregister_device(hr_dev);
  706. if (hr_dev->hw->hw_exit)
  707. hr_dev->hw->hw_exit(hr_dev);
  708. hns_roce_cleanup_bitmap(hr_dev);
  709. hns_roce_cleanup_hem(hr_dev);
  710. if (hr_dev->cmd_mod)
  711. hns_roce_cmd_use_polling(hr_dev);
  712. hr_dev->hw->cleanup_eq(hr_dev);
  713. hns_roce_cmd_cleanup(hr_dev);
  714. if (hr_dev->hw->cmq_exit)
  715. hr_dev->hw->cmq_exit(hr_dev);
  716. if (hr_dev->hw->reset)
  717. hr_dev->hw->reset(hr_dev, false);
  718. }
  719. EXPORT_SYMBOL_GPL(hns_roce_exit);
  720. MODULE_LICENSE("Dual BSD/GPL");
  721. MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
  722. MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
  723. MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
  724. MODULE_DESCRIPTION("HNS RoCE Driver");