hns_roce_cq.c 14 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/platform_device.h>
  33. #include <rdma/ib_umem.h>
  34. #include "hns_roce_device.h"
  35. #include "hns_roce_cmd.h"
  36. #include "hns_roce_hem.h"
  37. #include <rdma/hns-abi.h>
  38. #include "hns_roce_common.h"
  39. static void hns_roce_ib_cq_comp(struct hns_roce_cq *hr_cq)
  40. {
  41. struct ib_cq *ibcq = &hr_cq->ib_cq;
  42. ibcq->comp_handler(ibcq, ibcq->cq_context);
  43. }
  44. static void hns_roce_ib_cq_event(struct hns_roce_cq *hr_cq,
  45. enum hns_roce_event event_type)
  46. {
  47. struct hns_roce_dev *hr_dev;
  48. struct ib_event event;
  49. struct ib_cq *ibcq;
  50. ibcq = &hr_cq->ib_cq;
  51. hr_dev = to_hr_dev(ibcq->device);
  52. if (event_type != HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID &&
  53. event_type != HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR &&
  54. event_type != HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW) {
  55. dev_err(hr_dev->dev,
  56. "hns_roce_ib: Unexpected event type 0x%x on CQ %06lx\n",
  57. event_type, hr_cq->cqn);
  58. return;
  59. }
  60. if (ibcq->event_handler) {
  61. event.device = ibcq->device;
  62. event.event = IB_EVENT_CQ_ERR;
  63. event.element.cq = ibcq;
  64. ibcq->event_handler(&event, ibcq->cq_context);
  65. }
  66. }
  67. static int hns_roce_sw2hw_cq(struct hns_roce_dev *dev,
  68. struct hns_roce_cmd_mailbox *mailbox,
  69. unsigned long cq_num)
  70. {
  71. return hns_roce_cmd_mbox(dev, mailbox->dma, 0, cq_num, 0,
  72. HNS_ROCE_CMD_SW2HW_CQ, HNS_ROCE_CMD_TIMEOUT_MSECS);
  73. }
  74. static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent,
  75. struct hns_roce_mtt *hr_mtt,
  76. struct hns_roce_uar *hr_uar,
  77. struct hns_roce_cq *hr_cq, int vector)
  78. {
  79. struct hns_roce_cmd_mailbox *mailbox;
  80. struct hns_roce_hem_table *mtt_table;
  81. struct hns_roce_cq_table *cq_table;
  82. struct device *dev = hr_dev->dev;
  83. dma_addr_t dma_handle;
  84. u64 *mtts;
  85. int ret;
  86. cq_table = &hr_dev->cq_table;
  87. /* Get the physical address of cq buf */
  88. if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
  89. mtt_table = &hr_dev->mr_table.mtt_cqe_table;
  90. else
  91. mtt_table = &hr_dev->mr_table.mtt_table;
  92. mtts = hns_roce_table_find(hr_dev, mtt_table,
  93. hr_mtt->first_seg, &dma_handle);
  94. if (!mtts) {
  95. dev_err(dev, "CQ alloc.Failed to find cq buf addr.\n");
  96. return -EINVAL;
  97. }
  98. if (vector >= hr_dev->caps.num_comp_vectors) {
  99. dev_err(dev, "CQ alloc.Invalid vector.\n");
  100. return -EINVAL;
  101. }
  102. hr_cq->vector = vector;
  103. ret = hns_roce_bitmap_alloc(&cq_table->bitmap, &hr_cq->cqn);
  104. if (ret == -1) {
  105. dev_err(dev, "CQ alloc.Failed to alloc index.\n");
  106. return -ENOMEM;
  107. }
  108. /* Get CQC memory HEM(Hardware Entry Memory) table */
  109. ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn);
  110. if (ret) {
  111. dev_err(dev, "CQ alloc.Failed to get context mem.\n");
  112. goto err_out;
  113. }
  114. /* The cq insert radix tree */
  115. spin_lock_irq(&cq_table->lock);
  116. /* Radix_tree: The associated pointer and long integer key value like */
  117. ret = radix_tree_insert(&cq_table->tree, hr_cq->cqn, hr_cq);
  118. spin_unlock_irq(&cq_table->lock);
  119. if (ret) {
  120. dev_err(dev, "CQ alloc.Failed to radix_tree_insert.\n");
  121. goto err_put;
  122. }
  123. /* Allocate mailbox memory */
  124. mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
  125. if (IS_ERR(mailbox)) {
  126. ret = PTR_ERR(mailbox);
  127. goto err_radix;
  128. }
  129. hr_dev->hw->write_cqc(hr_dev, hr_cq, mailbox->buf, mtts, dma_handle,
  130. nent, vector);
  131. /* Send mailbox to hw */
  132. ret = hns_roce_sw2hw_cq(hr_dev, mailbox, hr_cq->cqn);
  133. hns_roce_free_cmd_mailbox(hr_dev, mailbox);
  134. if (ret) {
  135. dev_err(dev, "CQ alloc.Failed to cmd mailbox.\n");
  136. goto err_radix;
  137. }
  138. hr_cq->cons_index = 0;
  139. hr_cq->arm_sn = 1;
  140. hr_cq->uar = hr_uar;
  141. atomic_set(&hr_cq->refcount, 1);
  142. init_completion(&hr_cq->free);
  143. return 0;
  144. err_radix:
  145. spin_lock_irq(&cq_table->lock);
  146. radix_tree_delete(&cq_table->tree, hr_cq->cqn);
  147. spin_unlock_irq(&cq_table->lock);
  148. err_put:
  149. hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
  150. err_out:
  151. hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
  152. return ret;
  153. }
  154. static int hns_roce_hw2sw_cq(struct hns_roce_dev *dev,
  155. struct hns_roce_cmd_mailbox *mailbox,
  156. unsigned long cq_num)
  157. {
  158. return hns_roce_cmd_mbox(dev, 0, mailbox ? mailbox->dma : 0, cq_num,
  159. mailbox ? 0 : 1, HNS_ROCE_CMD_HW2SW_CQ,
  160. HNS_ROCE_CMD_TIMEOUT_MSECS);
  161. }
  162. void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
  163. {
  164. struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
  165. struct device *dev = hr_dev->dev;
  166. int ret;
  167. ret = hns_roce_hw2sw_cq(hr_dev, NULL, hr_cq->cqn);
  168. if (ret)
  169. dev_err(dev, "HW2SW_CQ failed (%d) for CQN %06lx\n", ret,
  170. hr_cq->cqn);
  171. /* Waiting interrupt process procedure carried out */
  172. synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq);
  173. /* wait for all interrupt processed */
  174. if (atomic_dec_and_test(&hr_cq->refcount))
  175. complete(&hr_cq->free);
  176. wait_for_completion(&hr_cq->free);
  177. spin_lock_irq(&cq_table->lock);
  178. radix_tree_delete(&cq_table->tree, hr_cq->cqn);
  179. spin_unlock_irq(&cq_table->lock);
  180. hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
  181. hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
  182. }
  183. EXPORT_SYMBOL_GPL(hns_roce_free_cq);
  184. static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev,
  185. struct ib_ucontext *context,
  186. struct hns_roce_cq_buf *buf,
  187. struct ib_umem **umem, u64 buf_addr, int cqe)
  188. {
  189. int ret;
  190. u32 page_shift;
  191. u32 npages;
  192. *umem = ib_umem_get(context, buf_addr, cqe * hr_dev->caps.cq_entry_sz,
  193. IB_ACCESS_LOCAL_WRITE, 1);
  194. if (IS_ERR(*umem))
  195. return PTR_ERR(*umem);
  196. if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
  197. buf->hr_mtt.mtt_type = MTT_TYPE_CQE;
  198. else
  199. buf->hr_mtt.mtt_type = MTT_TYPE_WQE;
  200. if (hr_dev->caps.cqe_buf_pg_sz) {
  201. npages = (ib_umem_page_count(*umem) +
  202. (1 << hr_dev->caps.cqe_buf_pg_sz) - 1) /
  203. (1 << hr_dev->caps.cqe_buf_pg_sz);
  204. page_shift = PAGE_SHIFT + hr_dev->caps.cqe_buf_pg_sz;
  205. ret = hns_roce_mtt_init(hr_dev, npages, page_shift,
  206. &buf->hr_mtt);
  207. } else {
  208. ret = hns_roce_mtt_init(hr_dev, ib_umem_page_count(*umem),
  209. (*umem)->page_shift,
  210. &buf->hr_mtt);
  211. }
  212. if (ret)
  213. goto err_buf;
  214. ret = hns_roce_ib_umem_write_mtt(hr_dev, &buf->hr_mtt, *umem);
  215. if (ret)
  216. goto err_mtt;
  217. return 0;
  218. err_mtt:
  219. hns_roce_mtt_cleanup(hr_dev, &buf->hr_mtt);
  220. err_buf:
  221. ib_umem_release(*umem);
  222. return ret;
  223. }
  224. static int hns_roce_ib_alloc_cq_buf(struct hns_roce_dev *hr_dev,
  225. struct hns_roce_cq_buf *buf, u32 nent)
  226. {
  227. int ret;
  228. u32 page_shift = PAGE_SHIFT + hr_dev->caps.cqe_buf_pg_sz;
  229. ret = hns_roce_buf_alloc(hr_dev, nent * hr_dev->caps.cq_entry_sz,
  230. (1 << page_shift) * 2, &buf->hr_buf,
  231. page_shift);
  232. if (ret)
  233. goto out;
  234. if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
  235. buf->hr_mtt.mtt_type = MTT_TYPE_CQE;
  236. else
  237. buf->hr_mtt.mtt_type = MTT_TYPE_WQE;
  238. ret = hns_roce_mtt_init(hr_dev, buf->hr_buf.npages,
  239. buf->hr_buf.page_shift, &buf->hr_mtt);
  240. if (ret)
  241. goto err_buf;
  242. ret = hns_roce_buf_write_mtt(hr_dev, &buf->hr_mtt, &buf->hr_buf);
  243. if (ret)
  244. goto err_mtt;
  245. return 0;
  246. err_mtt:
  247. hns_roce_mtt_cleanup(hr_dev, &buf->hr_mtt);
  248. err_buf:
  249. hns_roce_buf_free(hr_dev, nent * hr_dev->caps.cq_entry_sz,
  250. &buf->hr_buf);
  251. out:
  252. return ret;
  253. }
  254. static void hns_roce_ib_free_cq_buf(struct hns_roce_dev *hr_dev,
  255. struct hns_roce_cq_buf *buf, int cqe)
  256. {
  257. hns_roce_buf_free(hr_dev, (cqe + 1) * hr_dev->caps.cq_entry_sz,
  258. &buf->hr_buf);
  259. }
  260. struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
  261. const struct ib_cq_init_attr *attr,
  262. struct ib_ucontext *context,
  263. struct ib_udata *udata)
  264. {
  265. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  266. struct device *dev = hr_dev->dev;
  267. struct hns_roce_ib_create_cq ucmd;
  268. struct hns_roce_ib_create_cq_resp resp = {};
  269. struct hns_roce_cq *hr_cq = NULL;
  270. struct hns_roce_uar *uar = NULL;
  271. int vector = attr->comp_vector;
  272. int cq_entries = attr->cqe;
  273. int ret;
  274. if (cq_entries < 1 || cq_entries > hr_dev->caps.max_cqes) {
  275. dev_err(dev, "Creat CQ failed. entries=%d, max=%d\n",
  276. cq_entries, hr_dev->caps.max_cqes);
  277. return ERR_PTR(-EINVAL);
  278. }
  279. hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL);
  280. if (!hr_cq)
  281. return ERR_PTR(-ENOMEM);
  282. if (hr_dev->caps.min_cqes)
  283. cq_entries = max(cq_entries, hr_dev->caps.min_cqes);
  284. cq_entries = roundup_pow_of_two((unsigned int)cq_entries);
  285. hr_cq->ib_cq.cqe = cq_entries - 1;
  286. spin_lock_init(&hr_cq->lock);
  287. if (context) {
  288. if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
  289. dev_err(dev, "Failed to copy_from_udata.\n");
  290. ret = -EFAULT;
  291. goto err_cq;
  292. }
  293. /* Get user space address, write it into mtt table */
  294. ret = hns_roce_ib_get_cq_umem(hr_dev, context, &hr_cq->hr_buf,
  295. &hr_cq->umem, ucmd.buf_addr,
  296. cq_entries);
  297. if (ret) {
  298. dev_err(dev, "Failed to get_cq_umem.\n");
  299. goto err_cq;
  300. }
  301. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  302. (udata->outlen >= sizeof(resp))) {
  303. ret = hns_roce_db_map_user(to_hr_ucontext(context),
  304. ucmd.db_addr, &hr_cq->db);
  305. if (ret) {
  306. dev_err(dev, "cq record doorbell map failed!\n");
  307. goto err_mtt;
  308. }
  309. hr_cq->db_en = 1;
  310. resp.cap_flags |= HNS_ROCE_SUPPORT_CQ_RECORD_DB;
  311. }
  312. /* Get user space parameters */
  313. uar = &to_hr_ucontext(context)->uar;
  314. } else {
  315. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
  316. ret = hns_roce_alloc_db(hr_dev, &hr_cq->db, 1);
  317. if (ret)
  318. goto err_cq;
  319. hr_cq->set_ci_db = hr_cq->db.db_record;
  320. *hr_cq->set_ci_db = 0;
  321. hr_cq->db_en = 1;
  322. }
  323. /* Init mmt table and write buff address to mtt table */
  324. ret = hns_roce_ib_alloc_cq_buf(hr_dev, &hr_cq->hr_buf,
  325. cq_entries);
  326. if (ret) {
  327. dev_err(dev, "Failed to alloc_cq_buf.\n");
  328. goto err_db;
  329. }
  330. uar = &hr_dev->priv_uar;
  331. hr_cq->cq_db_l = hr_dev->reg_base + hr_dev->odb_offset +
  332. DB_REG_OFFSET * uar->index;
  333. }
  334. /* Allocate cq index, fill cq_context */
  335. ret = hns_roce_cq_alloc(hr_dev, cq_entries, &hr_cq->hr_buf.hr_mtt, uar,
  336. hr_cq, vector);
  337. if (ret) {
  338. dev_err(dev, "Creat CQ .Failed to cq_alloc.\n");
  339. goto err_dbmap;
  340. }
  341. /*
  342. * For the QP created by kernel space, tptr value should be initialized
  343. * to zero; For the QP created by user space, it will cause synchronous
  344. * problems if tptr is set to zero here, so we initialze it in user
  345. * space.
  346. */
  347. if (!context && hr_cq->tptr_addr)
  348. *hr_cq->tptr_addr = 0;
  349. /* Get created cq handler and carry out event */
  350. hr_cq->comp = hns_roce_ib_cq_comp;
  351. hr_cq->event = hns_roce_ib_cq_event;
  352. hr_cq->cq_depth = cq_entries;
  353. if (context) {
  354. resp.cqn = hr_cq->cqn;
  355. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  356. if (ret)
  357. goto err_cqc;
  358. }
  359. return &hr_cq->ib_cq;
  360. err_cqc:
  361. hns_roce_free_cq(hr_dev, hr_cq);
  362. err_dbmap:
  363. if (context && (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  364. (udata->outlen >= sizeof(resp)))
  365. hns_roce_db_unmap_user(to_hr_ucontext(context),
  366. &hr_cq->db);
  367. err_mtt:
  368. hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
  369. if (context)
  370. ib_umem_release(hr_cq->umem);
  371. else
  372. hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf,
  373. hr_cq->ib_cq.cqe);
  374. err_db:
  375. if (!context && (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB))
  376. hns_roce_free_db(hr_dev, &hr_cq->db);
  377. err_cq:
  378. kfree(hr_cq);
  379. return ERR_PTR(ret);
  380. }
  381. EXPORT_SYMBOL_GPL(hns_roce_ib_create_cq);
  382. int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq)
  383. {
  384. struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device);
  385. struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq);
  386. int ret = 0;
  387. if (hr_dev->hw->destroy_cq) {
  388. ret = hr_dev->hw->destroy_cq(ib_cq);
  389. } else {
  390. hns_roce_free_cq(hr_dev, hr_cq);
  391. hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
  392. if (ib_cq->uobject) {
  393. ib_umem_release(hr_cq->umem);
  394. if (hr_cq->db_en == 1)
  395. hns_roce_db_unmap_user(
  396. to_hr_ucontext(ib_cq->uobject->context),
  397. &hr_cq->db);
  398. } else {
  399. /* Free the buff of stored cq */
  400. hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf,
  401. ib_cq->cqe);
  402. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)
  403. hns_roce_free_db(hr_dev, &hr_cq->db);
  404. }
  405. kfree(hr_cq);
  406. }
  407. return ret;
  408. }
  409. EXPORT_SYMBOL_GPL(hns_roce_ib_destroy_cq);
  410. void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn)
  411. {
  412. struct device *dev = hr_dev->dev;
  413. struct hns_roce_cq *cq;
  414. cq = radix_tree_lookup(&hr_dev->cq_table.tree,
  415. cqn & (hr_dev->caps.num_cqs - 1));
  416. if (!cq) {
  417. dev_warn(dev, "Completion event for bogus CQ 0x%08x\n", cqn);
  418. return;
  419. }
  420. ++cq->arm_sn;
  421. cq->comp(cq);
  422. }
  423. EXPORT_SYMBOL_GPL(hns_roce_cq_completion);
  424. void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type)
  425. {
  426. struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
  427. struct device *dev = hr_dev->dev;
  428. struct hns_roce_cq *cq;
  429. cq = radix_tree_lookup(&cq_table->tree,
  430. cqn & (hr_dev->caps.num_cqs - 1));
  431. if (cq)
  432. atomic_inc(&cq->refcount);
  433. if (!cq) {
  434. dev_warn(dev, "Async event for bogus CQ %08x\n", cqn);
  435. return;
  436. }
  437. cq->event(cq, (enum hns_roce_event)event_type);
  438. if (atomic_dec_and_test(&cq->refcount))
  439. complete(&cq->free);
  440. }
  441. EXPORT_SYMBOL_GPL(hns_roce_cq_event);
  442. int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev)
  443. {
  444. struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
  445. spin_lock_init(&cq_table->lock);
  446. INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
  447. return hns_roce_bitmap_init(&cq_table->bitmap, hr_dev->caps.num_cqs,
  448. hr_dev->caps.num_cqs - 1,
  449. hr_dev->caps.reserved_cqs, 0);
  450. }
  451. void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev)
  452. {
  453. hns_roce_bitmap_cleanup(&hr_dev->cq_table.bitmap);
  454. }