vc4_irq.c 8.2 KB

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  1. /*
  2. * Copyright © 2014 Broadcom
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. */
  23. /**
  24. * DOC: Interrupt management for the V3D engine
  25. *
  26. * We have an interrupt status register (V3D_INTCTL) which reports
  27. * interrupts, and where writing 1 bits clears those interrupts.
  28. * There are also a pair of interrupt registers
  29. * (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
  30. * disables that specific interrupt, and 0s written are ignored
  31. * (reading either one returns the set of enabled interrupts).
  32. *
  33. * When we take a binning flush done interrupt, we need to submit the
  34. * next frame for binning and move the finished frame to the render
  35. * thread.
  36. *
  37. * When we take a render frame interrupt, we need to wake the
  38. * processes waiting for some frame to be done, and get the next frame
  39. * submitted ASAP (so the hardware doesn't sit idle when there's work
  40. * to do).
  41. *
  42. * When we take the binner out of memory interrupt, we need to
  43. * allocate some new memory and pass it to the binner so that the
  44. * current job can make progress.
  45. */
  46. #include "vc4_drv.h"
  47. #include "vc4_regs.h"
  48. #define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
  49. V3D_INT_FLDONE | \
  50. V3D_INT_FRDONE)
  51. DECLARE_WAIT_QUEUE_HEAD(render_wait);
  52. static void
  53. vc4_overflow_mem_work(struct work_struct *work)
  54. {
  55. struct vc4_dev *vc4 =
  56. container_of(work, struct vc4_dev, overflow_mem_work);
  57. struct vc4_bo *bo = vc4->bin_bo;
  58. int bin_bo_slot;
  59. struct vc4_exec_info *exec;
  60. unsigned long irqflags;
  61. bin_bo_slot = vc4_v3d_get_bin_slot(vc4);
  62. if (bin_bo_slot < 0) {
  63. DRM_ERROR("Couldn't allocate binner overflow mem\n");
  64. return;
  65. }
  66. spin_lock_irqsave(&vc4->job_lock, irqflags);
  67. if (vc4->bin_alloc_overflow) {
  68. /* If we had overflow memory allocated previously,
  69. * then that chunk will free when the current bin job
  70. * is done. If we don't have a bin job running, then
  71. * the chunk will be done whenever the list of render
  72. * jobs has drained.
  73. */
  74. exec = vc4_first_bin_job(vc4);
  75. if (!exec)
  76. exec = vc4_last_render_job(vc4);
  77. if (exec) {
  78. exec->bin_slots |= vc4->bin_alloc_overflow;
  79. } else {
  80. /* There's nothing queued in the hardware, so
  81. * the old slot is free immediately.
  82. */
  83. vc4->bin_alloc_used &= ~vc4->bin_alloc_overflow;
  84. }
  85. }
  86. vc4->bin_alloc_overflow = BIT(bin_bo_slot);
  87. V3D_WRITE(V3D_BPOA, bo->base.paddr + bin_bo_slot * vc4->bin_alloc_size);
  88. V3D_WRITE(V3D_BPOS, bo->base.base.size);
  89. V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
  90. V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
  91. spin_unlock_irqrestore(&vc4->job_lock, irqflags);
  92. }
  93. static void
  94. vc4_irq_finish_bin_job(struct drm_device *dev)
  95. {
  96. struct vc4_dev *vc4 = to_vc4_dev(dev);
  97. struct vc4_exec_info *next, *exec = vc4_first_bin_job(vc4);
  98. if (!exec)
  99. return;
  100. vc4_move_job_to_render(dev, exec);
  101. next = vc4_first_bin_job(vc4);
  102. /* Only submit the next job in the bin list if it matches the perfmon
  103. * attached to the one that just finished (or if both jobs don't have
  104. * perfmon attached to them).
  105. */
  106. if (next && next->perfmon == exec->perfmon)
  107. vc4_submit_next_bin_job(dev);
  108. }
  109. static void
  110. vc4_cancel_bin_job(struct drm_device *dev)
  111. {
  112. struct vc4_dev *vc4 = to_vc4_dev(dev);
  113. struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
  114. if (!exec)
  115. return;
  116. /* Stop the perfmon so that the next bin job can be started. */
  117. if (exec->perfmon)
  118. vc4_perfmon_stop(vc4, exec->perfmon, false);
  119. list_move_tail(&exec->head, &vc4->bin_job_list);
  120. vc4_submit_next_bin_job(dev);
  121. }
  122. static void
  123. vc4_irq_finish_render_job(struct drm_device *dev)
  124. {
  125. struct vc4_dev *vc4 = to_vc4_dev(dev);
  126. struct vc4_exec_info *exec = vc4_first_render_job(vc4);
  127. struct vc4_exec_info *nextbin, *nextrender;
  128. if (!exec)
  129. return;
  130. vc4->finished_seqno++;
  131. list_move_tail(&exec->head, &vc4->job_done_list);
  132. nextbin = vc4_first_bin_job(vc4);
  133. nextrender = vc4_first_render_job(vc4);
  134. /* Only stop the perfmon if following jobs in the queue don't expect it
  135. * to be enabled.
  136. */
  137. if (exec->perfmon && !nextrender &&
  138. (!nextbin || nextbin->perfmon != exec->perfmon))
  139. vc4_perfmon_stop(vc4, exec->perfmon, true);
  140. /* If there's a render job waiting, start it. If this is not the case
  141. * we may have to unblock the binner if it's been stalled because of
  142. * perfmon (this can be checked by comparing the perfmon attached to
  143. * the finished renderjob to the one attached to the next bin job: if
  144. * they don't match, this means the binner is stalled and should be
  145. * restarted).
  146. */
  147. if (nextrender)
  148. vc4_submit_next_render_job(dev);
  149. else if (nextbin && nextbin->perfmon != exec->perfmon)
  150. vc4_submit_next_bin_job(dev);
  151. if (exec->fence) {
  152. dma_fence_signal_locked(exec->fence);
  153. dma_fence_put(exec->fence);
  154. exec->fence = NULL;
  155. }
  156. wake_up_all(&vc4->job_wait_queue);
  157. schedule_work(&vc4->job_done_work);
  158. }
  159. irqreturn_t
  160. vc4_irq(int irq, void *arg)
  161. {
  162. struct drm_device *dev = arg;
  163. struct vc4_dev *vc4 = to_vc4_dev(dev);
  164. uint32_t intctl;
  165. irqreturn_t status = IRQ_NONE;
  166. barrier();
  167. intctl = V3D_READ(V3D_INTCTL);
  168. /* Acknowledge the interrupts we're handling here. The binner
  169. * last flush / render frame done interrupt will be cleared,
  170. * while OUTOMEM will stay high until the underlying cause is
  171. * cleared.
  172. */
  173. V3D_WRITE(V3D_INTCTL, intctl);
  174. if (intctl & V3D_INT_OUTOMEM) {
  175. /* Disable OUTOMEM until the work is done. */
  176. V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
  177. schedule_work(&vc4->overflow_mem_work);
  178. status = IRQ_HANDLED;
  179. }
  180. if (intctl & V3D_INT_FLDONE) {
  181. spin_lock(&vc4->job_lock);
  182. vc4_irq_finish_bin_job(dev);
  183. spin_unlock(&vc4->job_lock);
  184. status = IRQ_HANDLED;
  185. }
  186. if (intctl & V3D_INT_FRDONE) {
  187. spin_lock(&vc4->job_lock);
  188. vc4_irq_finish_render_job(dev);
  189. spin_unlock(&vc4->job_lock);
  190. status = IRQ_HANDLED;
  191. }
  192. return status;
  193. }
  194. void
  195. vc4_irq_preinstall(struct drm_device *dev)
  196. {
  197. struct vc4_dev *vc4 = to_vc4_dev(dev);
  198. init_waitqueue_head(&vc4->job_wait_queue);
  199. INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);
  200. /* Clear any pending interrupts someone might have left around
  201. * for us.
  202. */
  203. V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
  204. }
  205. int
  206. vc4_irq_postinstall(struct drm_device *dev)
  207. {
  208. struct vc4_dev *vc4 = to_vc4_dev(dev);
  209. /* Enable both the render done and out of memory interrupts. */
  210. V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
  211. return 0;
  212. }
  213. void
  214. vc4_irq_uninstall(struct drm_device *dev)
  215. {
  216. struct vc4_dev *vc4 = to_vc4_dev(dev);
  217. /* Disable sending interrupts for our driver's IRQs. */
  218. V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);
  219. /* Clear any pending interrupts we might have left. */
  220. V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
  221. /* Finish any interrupt handler still in flight. */
  222. disable_irq(dev->irq);
  223. cancel_work_sync(&vc4->overflow_mem_work);
  224. }
  225. /** Reinitializes interrupt registers when a GPU reset is performed. */
  226. void vc4_irq_reset(struct drm_device *dev)
  227. {
  228. struct vc4_dev *vc4 = to_vc4_dev(dev);
  229. unsigned long irqflags;
  230. /* Acknowledge any stale IRQs. */
  231. V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
  232. /*
  233. * Turn all our interrupts on. Binner out of memory is the
  234. * only one we expect to trigger at this point, since we've
  235. * just come from poweron and haven't supplied any overflow
  236. * memory yet.
  237. */
  238. V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
  239. spin_lock_irqsave(&vc4->job_lock, irqflags);
  240. vc4_cancel_bin_job(dev);
  241. vc4_irq_finish_render_job(dev);
  242. spin_unlock_irqrestore(&vc4->job_lock, irqflags);
  243. }