sdi.c 8.5 KB

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  1. /*
  2. * Copyright (C) 2009 Nokia Corporation
  3. * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #define DSS_SUBSYS_NAME "SDI"
  18. #include <linux/kernel.h>
  19. #include <linux/delay.h>
  20. #include <linux/err.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/export.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/string.h>
  25. #include <linux/of.h>
  26. #include "omapdss.h"
  27. #include "dss.h"
  28. struct sdi_device {
  29. struct platform_device *pdev;
  30. struct dss_device *dss;
  31. bool update_enabled;
  32. struct regulator *vdds_sdi_reg;
  33. struct dss_lcd_mgr_config mgr_config;
  34. struct videomode vm;
  35. int datapairs;
  36. struct omap_dss_device output;
  37. };
  38. #define dssdev_to_sdi(dssdev) container_of(dssdev, struct sdi_device, output)
  39. struct sdi_clk_calc_ctx {
  40. struct sdi_device *sdi;
  41. unsigned long pck_min, pck_max;
  42. unsigned long fck;
  43. struct dispc_clock_info dispc_cinfo;
  44. };
  45. static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
  46. unsigned long pck, void *data)
  47. {
  48. struct sdi_clk_calc_ctx *ctx = data;
  49. ctx->dispc_cinfo.lck_div = lckd;
  50. ctx->dispc_cinfo.pck_div = pckd;
  51. ctx->dispc_cinfo.lck = lck;
  52. ctx->dispc_cinfo.pck = pck;
  53. return true;
  54. }
  55. static bool dpi_calc_dss_cb(unsigned long fck, void *data)
  56. {
  57. struct sdi_clk_calc_ctx *ctx = data;
  58. ctx->fck = fck;
  59. return dispc_div_calc(ctx->sdi->dss->dispc, fck,
  60. ctx->pck_min, ctx->pck_max,
  61. dpi_calc_dispc_cb, ctx);
  62. }
  63. static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk,
  64. unsigned long *fck,
  65. struct dispc_clock_info *dispc_cinfo)
  66. {
  67. int i;
  68. struct sdi_clk_calc_ctx ctx;
  69. /*
  70. * DSS fclk gives us very few possibilities, so finding a good pixel
  71. * clock may not be possible. We try multiple times to find the clock,
  72. * each time widening the pixel clock range we look for, up to
  73. * +/- 1MHz.
  74. */
  75. for (i = 0; i < 10; ++i) {
  76. bool ok;
  77. memset(&ctx, 0, sizeof(ctx));
  78. ctx.sdi = sdi;
  79. if (pclk > 1000 * i * i * i)
  80. ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
  81. else
  82. ctx.pck_min = 0;
  83. ctx.pck_max = pclk + 1000 * i * i * i;
  84. ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min,
  85. dpi_calc_dss_cb, &ctx);
  86. if (ok) {
  87. *fck = ctx.fck;
  88. *dispc_cinfo = ctx.dispc_cinfo;
  89. return 0;
  90. }
  91. }
  92. return -EINVAL;
  93. }
  94. static void sdi_config_lcd_manager(struct sdi_device *sdi)
  95. {
  96. sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
  97. sdi->mgr_config.stallmode = false;
  98. sdi->mgr_config.fifohandcheck = false;
  99. sdi->mgr_config.video_port_width = 24;
  100. sdi->mgr_config.lcden_sig_polarity = 1;
  101. dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config);
  102. }
  103. static int sdi_display_enable(struct omap_dss_device *dssdev)
  104. {
  105. struct sdi_device *sdi = dssdev_to_sdi(dssdev);
  106. struct dispc_clock_info dispc_cinfo;
  107. unsigned long fck;
  108. int r;
  109. if (!sdi->output.dispc_channel_connected) {
  110. DSSERR("failed to enable display: no output/manager\n");
  111. return -ENODEV;
  112. }
  113. r = regulator_enable(sdi->vdds_sdi_reg);
  114. if (r)
  115. goto err_reg_enable;
  116. r = dispc_runtime_get(sdi->dss->dispc);
  117. if (r)
  118. goto err_get_dispc;
  119. r = sdi_calc_clock_div(sdi, sdi->vm.pixelclock, &fck, &dispc_cinfo);
  120. if (r)
  121. goto err_calc_clock_div;
  122. sdi->mgr_config.clock_info = dispc_cinfo;
  123. r = dss_set_fck_rate(sdi->dss, fck);
  124. if (r)
  125. goto err_set_dss_clock_div;
  126. sdi_config_lcd_manager(sdi);
  127. /*
  128. * LCLK and PCLK divisors are located in shadow registers, and we
  129. * normally write them to DISPC registers when enabling the output.
  130. * However, SDI uses pck-free as source clock for its PLL, and pck-free
  131. * is affected by the divisors. And as we need the PLL before enabling
  132. * the output, we need to write the divisors early.
  133. *
  134. * It seems just writing to the DISPC register is enough, and we don't
  135. * need to care about the shadow register mechanism for pck-free. The
  136. * exact reason for this is unknown.
  137. */
  138. dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel,
  139. &sdi->mgr_config.clock_info);
  140. dss_sdi_init(sdi->dss, sdi->datapairs);
  141. r = dss_sdi_enable(sdi->dss);
  142. if (r)
  143. goto err_sdi_enable;
  144. mdelay(2);
  145. r = dss_mgr_enable(&sdi->output);
  146. if (r)
  147. goto err_mgr_enable;
  148. return 0;
  149. err_mgr_enable:
  150. dss_sdi_disable(sdi->dss);
  151. err_sdi_enable:
  152. err_set_dss_clock_div:
  153. err_calc_clock_div:
  154. dispc_runtime_put(sdi->dss->dispc);
  155. err_get_dispc:
  156. regulator_disable(sdi->vdds_sdi_reg);
  157. err_reg_enable:
  158. return r;
  159. }
  160. static void sdi_display_disable(struct omap_dss_device *dssdev)
  161. {
  162. struct sdi_device *sdi = dssdev_to_sdi(dssdev);
  163. dss_mgr_disable(&sdi->output);
  164. dss_sdi_disable(sdi->dss);
  165. dispc_runtime_put(sdi->dss->dispc);
  166. regulator_disable(sdi->vdds_sdi_reg);
  167. }
  168. static void sdi_set_timings(struct omap_dss_device *dssdev,
  169. const struct videomode *vm)
  170. {
  171. struct sdi_device *sdi = dssdev_to_sdi(dssdev);
  172. sdi->vm = *vm;
  173. }
  174. static int sdi_check_timings(struct omap_dss_device *dssdev,
  175. struct videomode *vm)
  176. {
  177. struct sdi_device *sdi = dssdev_to_sdi(dssdev);
  178. struct dispc_clock_info dispc_cinfo;
  179. unsigned long fck;
  180. unsigned long pck;
  181. int r;
  182. if (vm->pixelclock == 0)
  183. return -EINVAL;
  184. r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo);
  185. if (r)
  186. return r;
  187. pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
  188. if (pck != vm->pixelclock) {
  189. DSSWARN("Pixel clock adjusted from %lu Hz to %lu Hz\n",
  190. vm->pixelclock, pck);
  191. vm->pixelclock = pck;
  192. }
  193. return 0;
  194. }
  195. static int sdi_connect(struct omap_dss_device *src,
  196. struct omap_dss_device *dst)
  197. {
  198. int r;
  199. r = omapdss_device_connect(dst->dss, dst, dst->next);
  200. if (r)
  201. return r;
  202. dst->dispc_channel_connected = true;
  203. return 0;
  204. }
  205. static void sdi_disconnect(struct omap_dss_device *src,
  206. struct omap_dss_device *dst)
  207. {
  208. dst->dispc_channel_connected = false;
  209. omapdss_device_disconnect(dst, dst->next);
  210. }
  211. static const struct omap_dss_device_ops sdi_ops = {
  212. .connect = sdi_connect,
  213. .disconnect = sdi_disconnect,
  214. .enable = sdi_display_enable,
  215. .disable = sdi_display_disable,
  216. .check_timings = sdi_check_timings,
  217. .set_timings = sdi_set_timings,
  218. };
  219. static int sdi_init_output(struct sdi_device *sdi)
  220. {
  221. struct omap_dss_device *out = &sdi->output;
  222. int r;
  223. out->dev = &sdi->pdev->dev;
  224. out->id = OMAP_DSS_OUTPUT_SDI;
  225. out->output_type = OMAP_DISPLAY_TYPE_SDI;
  226. out->name = "sdi.0";
  227. out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
  228. /* We have SDI only on OMAP3, where it's on port 1 */
  229. out->of_ports = BIT(1);
  230. out->ops = &sdi_ops;
  231. out->owner = THIS_MODULE;
  232. out->bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE /* 15.5.9.1.2 */
  233. | DRM_BUS_FLAG_SYNC_POSEDGE;
  234. out->next = omapdss_of_find_connected_device(out->dev->of_node, 1);
  235. if (IS_ERR(out->next)) {
  236. if (PTR_ERR(out->next) != -EPROBE_DEFER)
  237. dev_err(out->dev, "failed to find video sink\n");
  238. return PTR_ERR(out->next);
  239. }
  240. r = omapdss_output_validate(out);
  241. if (r) {
  242. omapdss_device_put(out->next);
  243. out->next = NULL;
  244. return r;
  245. }
  246. omapdss_device_register(out);
  247. return 0;
  248. }
  249. static void sdi_uninit_output(struct sdi_device *sdi)
  250. {
  251. if (sdi->output.next)
  252. omapdss_device_put(sdi->output.next);
  253. omapdss_device_unregister(&sdi->output);
  254. }
  255. int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
  256. struct device_node *port)
  257. {
  258. struct sdi_device *sdi;
  259. struct device_node *ep;
  260. u32 datapairs;
  261. int r;
  262. sdi = kzalloc(sizeof(*sdi), GFP_KERNEL);
  263. if (!sdi)
  264. return -ENOMEM;
  265. ep = of_get_next_child(port, NULL);
  266. if (!ep) {
  267. r = 0;
  268. goto err_free;
  269. }
  270. r = of_property_read_u32(ep, "datapairs", &datapairs);
  271. of_node_put(ep);
  272. if (r) {
  273. DSSERR("failed to parse datapairs\n");
  274. goto err_free;
  275. }
  276. sdi->datapairs = datapairs;
  277. sdi->dss = dss;
  278. sdi->pdev = pdev;
  279. port->data = sdi;
  280. sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi");
  281. if (IS_ERR(sdi->vdds_sdi_reg)) {
  282. r = PTR_ERR(sdi->vdds_sdi_reg);
  283. if (r != -EPROBE_DEFER)
  284. DSSERR("can't get VDDS_SDI regulator\n");
  285. goto err_free;
  286. }
  287. r = sdi_init_output(sdi);
  288. if (r)
  289. goto err_free;
  290. return 0;
  291. err_free:
  292. kfree(sdi);
  293. return r;
  294. }
  295. void sdi_uninit_port(struct device_node *port)
  296. {
  297. struct sdi_device *sdi = port->data;
  298. if (!sdi)
  299. return;
  300. sdi_uninit_output(sdi);
  301. kfree(sdi);
  302. }