dpu_hw_pingpong.c 5.8 KB

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  1. /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/iopoll.h>
  13. #include "dpu_hw_mdss.h"
  14. #include "dpu_hwio.h"
  15. #include "dpu_hw_catalog.h"
  16. #include "dpu_hw_pingpong.h"
  17. #include "dpu_dbg.h"
  18. #include "dpu_kms.h"
  19. #include "dpu_trace.h"
  20. #define PP_TEAR_CHECK_EN 0x000
  21. #define PP_SYNC_CONFIG_VSYNC 0x004
  22. #define PP_SYNC_CONFIG_HEIGHT 0x008
  23. #define PP_SYNC_WRCOUNT 0x00C
  24. #define PP_VSYNC_INIT_VAL 0x010
  25. #define PP_INT_COUNT_VAL 0x014
  26. #define PP_SYNC_THRESH 0x018
  27. #define PP_START_POS 0x01C
  28. #define PP_RD_PTR_IRQ 0x020
  29. #define PP_WR_PTR_IRQ 0x024
  30. #define PP_OUT_LINE_COUNT 0x028
  31. #define PP_LINE_COUNT 0x02C
  32. #define PP_FBC_MODE 0x034
  33. #define PP_FBC_BUDGET_CTL 0x038
  34. #define PP_FBC_LOSSY_MODE 0x03C
  35. static struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
  36. struct dpu_mdss_cfg *m,
  37. void __iomem *addr,
  38. struct dpu_hw_blk_reg_map *b)
  39. {
  40. int i;
  41. for (i = 0; i < m->pingpong_count; i++) {
  42. if (pp == m->pingpong[i].id) {
  43. b->base_off = addr;
  44. b->blk_off = m->pingpong[i].base;
  45. b->length = m->pingpong[i].len;
  46. b->hwversion = m->hwversion;
  47. b->log_mask = DPU_DBG_MASK_PINGPONG;
  48. return &m->pingpong[i];
  49. }
  50. }
  51. return ERR_PTR(-EINVAL);
  52. }
  53. static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp,
  54. struct dpu_hw_tear_check *te)
  55. {
  56. struct dpu_hw_blk_reg_map *c;
  57. int cfg;
  58. if (!pp || !te)
  59. return -EINVAL;
  60. c = &pp->hw;
  61. cfg = BIT(19); /*VSYNC_COUNTER_EN */
  62. if (te->hw_vsync_mode)
  63. cfg |= BIT(20);
  64. cfg |= te->vsync_count;
  65. DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
  66. DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
  67. DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);
  68. DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);
  69. DPU_REG_WRITE(c, PP_START_POS, te->start_pos);
  70. DPU_REG_WRITE(c, PP_SYNC_THRESH,
  71. ((te->sync_threshold_continue << 16) |
  72. te->sync_threshold_start));
  73. DPU_REG_WRITE(c, PP_SYNC_WRCOUNT,
  74. (te->start_pos + te->sync_threshold_start + 1));
  75. return 0;
  76. }
  77. static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp,
  78. u32 timeout_us)
  79. {
  80. struct dpu_hw_blk_reg_map *c;
  81. u32 val;
  82. int rc;
  83. if (!pp)
  84. return -EINVAL;
  85. c = &pp->hw;
  86. rc = readl_poll_timeout(c->base_off + c->blk_off + PP_LINE_COUNT,
  87. val, (val & 0xffff) >= 1, 10, timeout_us);
  88. return rc;
  89. }
  90. static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable)
  91. {
  92. struct dpu_hw_blk_reg_map *c;
  93. if (!pp)
  94. return -EINVAL;
  95. c = &pp->hw;
  96. DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable);
  97. return 0;
  98. }
  99. static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp,
  100. bool enable_external_te)
  101. {
  102. struct dpu_hw_blk_reg_map *c = &pp->hw;
  103. u32 cfg;
  104. int orig;
  105. if (!pp)
  106. return -EINVAL;
  107. c = &pp->hw;
  108. cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC);
  109. orig = (bool)(cfg & BIT(20));
  110. if (enable_external_te)
  111. cfg |= BIT(20);
  112. else
  113. cfg &= ~BIT(20);
  114. DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
  115. trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg);
  116. return orig;
  117. }
  118. static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp,
  119. struct dpu_hw_pp_vsync_info *info)
  120. {
  121. struct dpu_hw_blk_reg_map *c;
  122. u32 val;
  123. if (!pp || !info)
  124. return -EINVAL;
  125. c = &pp->hw;
  126. val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL);
  127. info->rd_ptr_init_val = val & 0xffff;
  128. val = DPU_REG_READ(c, PP_INT_COUNT_VAL);
  129. info->rd_ptr_frame_count = (val & 0xffff0000) >> 16;
  130. info->rd_ptr_line_count = val & 0xffff;
  131. val = DPU_REG_READ(c, PP_LINE_COUNT);
  132. info->wr_ptr_line_count = val & 0xffff;
  133. return 0;
  134. }
  135. static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
  136. {
  137. struct dpu_hw_blk_reg_map *c = &pp->hw;
  138. u32 height, init;
  139. u32 line = 0xFFFF;
  140. if (!pp)
  141. return 0;
  142. c = &pp->hw;
  143. init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF;
  144. height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;
  145. if (height < init)
  146. goto line_count_exit;
  147. line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;
  148. if (line < init)
  149. line += (0xFFFF - init);
  150. else
  151. line -= init;
  152. line_count_exit:
  153. return line;
  154. }
  155. static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops,
  156. const struct dpu_pingpong_cfg *hw_cap)
  157. {
  158. ops->setup_tearcheck = dpu_hw_pp_setup_te_config;
  159. ops->enable_tearcheck = dpu_hw_pp_enable_te;
  160. ops->connect_external_te = dpu_hw_pp_connect_external_te;
  161. ops->get_vsync_info = dpu_hw_pp_get_vsync_info;
  162. ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
  163. ops->get_line_count = dpu_hw_pp_get_line_count;
  164. };
  165. static struct dpu_hw_blk_ops dpu_hw_ops = {
  166. .start = NULL,
  167. .stop = NULL,
  168. };
  169. struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
  170. void __iomem *addr,
  171. struct dpu_mdss_cfg *m)
  172. {
  173. struct dpu_hw_pingpong *c;
  174. struct dpu_pingpong_cfg *cfg;
  175. int rc;
  176. c = kzalloc(sizeof(*c), GFP_KERNEL);
  177. if (!c)
  178. return ERR_PTR(-ENOMEM);
  179. cfg = _pingpong_offset(idx, m, addr, &c->hw);
  180. if (IS_ERR_OR_NULL(cfg)) {
  181. kfree(c);
  182. return ERR_PTR(-EINVAL);
  183. }
  184. c->idx = idx;
  185. c->caps = cfg;
  186. _setup_pingpong_ops(&c->ops, c->caps);
  187. rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops);
  188. if (rc) {
  189. DPU_ERROR("failed to init hw blk %d\n", rc);
  190. goto blk_init_error;
  191. }
  192. return c;
  193. blk_init_error:
  194. kzfree(c);
  195. return ERR_PTR(rc);
  196. }
  197. void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
  198. {
  199. if (pp)
  200. dpu_hw_blk_destroy(&pp->base);
  201. kfree(pp);
  202. }