mtk_drm_drv.c 17 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. * Author: YT SHEN <yt.shen@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <drm/drmP.h>
  15. #include <drm/drm_atomic.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_crtc_helper.h>
  18. #include <drm/drm_gem.h>
  19. #include <drm/drm_gem_cma_helper.h>
  20. #include <drm/drm_of.h>
  21. #include <linux/component.h>
  22. #include <linux/iommu.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/pm_runtime.h>
  26. #include "mtk_drm_crtc.h"
  27. #include "mtk_drm_ddp.h"
  28. #include "mtk_drm_ddp_comp.h"
  29. #include "mtk_drm_drv.h"
  30. #include "mtk_drm_fb.h"
  31. #include "mtk_drm_gem.h"
  32. #define DRIVER_NAME "mediatek"
  33. #define DRIVER_DESC "Mediatek SoC DRM"
  34. #define DRIVER_DATE "20150513"
  35. #define DRIVER_MAJOR 1
  36. #define DRIVER_MINOR 0
  37. static void mtk_atomic_schedule(struct mtk_drm_private *private,
  38. struct drm_atomic_state *state)
  39. {
  40. private->commit.state = state;
  41. schedule_work(&private->commit.work);
  42. }
  43. static void mtk_atomic_wait_for_fences(struct drm_atomic_state *state)
  44. {
  45. struct drm_plane *plane;
  46. struct drm_plane_state *new_plane_state;
  47. int i;
  48. for_each_new_plane_in_state(state, plane, new_plane_state, i)
  49. mtk_fb_wait(new_plane_state->fb);
  50. }
  51. static void mtk_atomic_complete(struct mtk_drm_private *private,
  52. struct drm_atomic_state *state)
  53. {
  54. struct drm_device *drm = private->drm;
  55. mtk_atomic_wait_for_fences(state);
  56. /*
  57. * Mediatek drm supports runtime PM, so plane registers cannot be
  58. * written when their crtc is disabled.
  59. *
  60. * The comment for drm_atomic_helper_commit states:
  61. * For drivers supporting runtime PM the recommended sequence is
  62. *
  63. * drm_atomic_helper_commit_modeset_disables(dev, state);
  64. * drm_atomic_helper_commit_modeset_enables(dev, state);
  65. * drm_atomic_helper_commit_planes(dev, state,
  66. * DRM_PLANE_COMMIT_ACTIVE_ONLY);
  67. *
  68. * See the kerneldoc entries for these three functions for more details.
  69. */
  70. drm_atomic_helper_commit_modeset_disables(drm, state);
  71. drm_atomic_helper_commit_modeset_enables(drm, state);
  72. drm_atomic_helper_commit_planes(drm, state,
  73. DRM_PLANE_COMMIT_ACTIVE_ONLY);
  74. drm_atomic_helper_wait_for_vblanks(drm, state);
  75. drm_atomic_helper_cleanup_planes(drm, state);
  76. drm_atomic_state_put(state);
  77. }
  78. static void mtk_atomic_work(struct work_struct *work)
  79. {
  80. struct mtk_drm_private *private = container_of(work,
  81. struct mtk_drm_private, commit.work);
  82. mtk_atomic_complete(private, private->commit.state);
  83. }
  84. static int mtk_atomic_commit(struct drm_device *drm,
  85. struct drm_atomic_state *state,
  86. bool async)
  87. {
  88. struct mtk_drm_private *private = drm->dev_private;
  89. int ret;
  90. ret = drm_atomic_helper_prepare_planes(drm, state);
  91. if (ret)
  92. return ret;
  93. mutex_lock(&private->commit.lock);
  94. flush_work(&private->commit.work);
  95. ret = drm_atomic_helper_swap_state(state, true);
  96. if (ret) {
  97. mutex_unlock(&private->commit.lock);
  98. drm_atomic_helper_cleanup_planes(drm, state);
  99. return ret;
  100. }
  101. drm_atomic_state_get(state);
  102. if (async)
  103. mtk_atomic_schedule(private, state);
  104. else
  105. mtk_atomic_complete(private, state);
  106. mutex_unlock(&private->commit.lock);
  107. return 0;
  108. }
  109. static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
  110. .fb_create = mtk_drm_mode_fb_create,
  111. .atomic_check = drm_atomic_helper_check,
  112. .atomic_commit = mtk_atomic_commit,
  113. };
  114. static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
  115. DDP_COMPONENT_OVL0,
  116. DDP_COMPONENT_RDMA0,
  117. DDP_COMPONENT_COLOR0,
  118. DDP_COMPONENT_BLS,
  119. DDP_COMPONENT_DSI0,
  120. };
  121. static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
  122. DDP_COMPONENT_RDMA1,
  123. DDP_COMPONENT_DPI0,
  124. };
  125. static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
  126. DDP_COMPONENT_OVL0,
  127. DDP_COMPONENT_COLOR0,
  128. DDP_COMPONENT_AAL0,
  129. DDP_COMPONENT_OD0,
  130. DDP_COMPONENT_RDMA0,
  131. DDP_COMPONENT_DPI0,
  132. DDP_COMPONENT_PWM0,
  133. };
  134. static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
  135. DDP_COMPONENT_OVL1,
  136. DDP_COMPONENT_COLOR1,
  137. DDP_COMPONENT_AAL1,
  138. DDP_COMPONENT_OD1,
  139. DDP_COMPONENT_RDMA1,
  140. DDP_COMPONENT_DPI1,
  141. DDP_COMPONENT_PWM1,
  142. };
  143. static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
  144. DDP_COMPONENT_RDMA2,
  145. DDP_COMPONENT_DSI3,
  146. DDP_COMPONENT_PWM2,
  147. };
  148. static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
  149. DDP_COMPONENT_OVL0,
  150. DDP_COMPONENT_COLOR0,
  151. DDP_COMPONENT_AAL0,
  152. DDP_COMPONENT_OD0,
  153. DDP_COMPONENT_RDMA0,
  154. DDP_COMPONENT_UFOE,
  155. DDP_COMPONENT_DSI0,
  156. DDP_COMPONENT_PWM0,
  157. };
  158. static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
  159. DDP_COMPONENT_OVL1,
  160. DDP_COMPONENT_COLOR1,
  161. DDP_COMPONENT_GAMMA,
  162. DDP_COMPONENT_RDMA1,
  163. DDP_COMPONENT_DPI0,
  164. };
  165. static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
  166. .main_path = mt2701_mtk_ddp_main,
  167. .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
  168. .ext_path = mt2701_mtk_ddp_ext,
  169. .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
  170. .shadow_register = true,
  171. };
  172. static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
  173. .main_path = mt2712_mtk_ddp_main,
  174. .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
  175. .ext_path = mt2712_mtk_ddp_ext,
  176. .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
  177. .third_path = mt2712_mtk_ddp_third,
  178. .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
  179. };
  180. static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
  181. .main_path = mt8173_mtk_ddp_main,
  182. .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
  183. .ext_path = mt8173_mtk_ddp_ext,
  184. .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
  185. };
  186. static int mtk_drm_kms_init(struct drm_device *drm)
  187. {
  188. struct mtk_drm_private *private = drm->dev_private;
  189. struct platform_device *pdev;
  190. struct device_node *np;
  191. int ret;
  192. if (!iommu_present(&platform_bus_type))
  193. return -EPROBE_DEFER;
  194. pdev = of_find_device_by_node(private->mutex_node);
  195. if (!pdev) {
  196. dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
  197. private->mutex_node);
  198. of_node_put(private->mutex_node);
  199. return -EPROBE_DEFER;
  200. }
  201. private->mutex_dev = &pdev->dev;
  202. drm_mode_config_init(drm);
  203. drm->mode_config.min_width = 64;
  204. drm->mode_config.min_height = 64;
  205. /*
  206. * set max width and height as default value(4096x4096).
  207. * this value would be used to check framebuffer size limitation
  208. * at drm_mode_addfb().
  209. */
  210. drm->mode_config.max_width = 4096;
  211. drm->mode_config.max_height = 4096;
  212. drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
  213. ret = component_bind_all(drm->dev, drm);
  214. if (ret)
  215. goto err_config_cleanup;
  216. /*
  217. * We currently support two fixed data streams, each optional,
  218. * and each statically assigned to a crtc:
  219. * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
  220. */
  221. ret = mtk_drm_crtc_create(drm, private->data->main_path,
  222. private->data->main_len);
  223. if (ret < 0)
  224. goto err_component_unbind;
  225. /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
  226. ret = mtk_drm_crtc_create(drm, private->data->ext_path,
  227. private->data->ext_len);
  228. if (ret < 0)
  229. goto err_component_unbind;
  230. ret = mtk_drm_crtc_create(drm, private->data->third_path,
  231. private->data->third_len);
  232. if (ret < 0)
  233. goto err_component_unbind;
  234. /* Use OVL device for all DMA memory allocations */
  235. np = private->comp_node[private->data->main_path[0]] ?:
  236. private->comp_node[private->data->ext_path[0]];
  237. pdev = of_find_device_by_node(np);
  238. if (!pdev) {
  239. ret = -ENODEV;
  240. dev_err(drm->dev, "Need at least one OVL device\n");
  241. goto err_component_unbind;
  242. }
  243. private->dma_dev = &pdev->dev;
  244. /*
  245. * We don't use the drm_irq_install() helpers provided by the DRM
  246. * core, so we need to set this manually in order to allow the
  247. * DRM_IOCTL_WAIT_VBLANK to operate correctly.
  248. */
  249. drm->irq_enabled = true;
  250. ret = drm_vblank_init(drm, MAX_CRTC);
  251. if (ret < 0)
  252. goto err_component_unbind;
  253. drm_kms_helper_poll_init(drm);
  254. drm_mode_config_reset(drm);
  255. return 0;
  256. err_component_unbind:
  257. component_unbind_all(drm->dev, drm);
  258. err_config_cleanup:
  259. drm_mode_config_cleanup(drm);
  260. return ret;
  261. }
  262. static void mtk_drm_kms_deinit(struct drm_device *drm)
  263. {
  264. drm_kms_helper_poll_fini(drm);
  265. component_unbind_all(drm->dev, drm);
  266. drm_mode_config_cleanup(drm);
  267. }
  268. static const struct file_operations mtk_drm_fops = {
  269. .owner = THIS_MODULE,
  270. .open = drm_open,
  271. .release = drm_release,
  272. .unlocked_ioctl = drm_ioctl,
  273. .mmap = mtk_drm_gem_mmap,
  274. .poll = drm_poll,
  275. .read = drm_read,
  276. .compat_ioctl = drm_compat_ioctl,
  277. };
  278. static struct drm_driver mtk_drm_driver = {
  279. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  280. DRIVER_ATOMIC,
  281. .gem_free_object_unlocked = mtk_drm_gem_free_object,
  282. .gem_vm_ops = &drm_gem_cma_vm_ops,
  283. .dumb_create = mtk_drm_gem_dumb_create,
  284. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  285. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  286. .gem_prime_export = drm_gem_prime_export,
  287. .gem_prime_import = drm_gem_prime_import,
  288. .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table,
  289. .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
  290. .gem_prime_mmap = mtk_drm_gem_mmap_buf,
  291. .fops = &mtk_drm_fops,
  292. .name = DRIVER_NAME,
  293. .desc = DRIVER_DESC,
  294. .date = DRIVER_DATE,
  295. .major = DRIVER_MAJOR,
  296. .minor = DRIVER_MINOR,
  297. };
  298. static int compare_of(struct device *dev, void *data)
  299. {
  300. return dev->of_node == data;
  301. }
  302. static int mtk_drm_bind(struct device *dev)
  303. {
  304. struct mtk_drm_private *private = dev_get_drvdata(dev);
  305. struct drm_device *drm;
  306. int ret;
  307. drm = drm_dev_alloc(&mtk_drm_driver, dev);
  308. if (IS_ERR(drm))
  309. return PTR_ERR(drm);
  310. drm->dev_private = private;
  311. private->drm = drm;
  312. ret = mtk_drm_kms_init(drm);
  313. if (ret < 0)
  314. goto err_free;
  315. ret = drm_dev_register(drm, 0);
  316. if (ret < 0)
  317. goto err_deinit;
  318. return 0;
  319. err_deinit:
  320. mtk_drm_kms_deinit(drm);
  321. err_free:
  322. drm_dev_put(drm);
  323. return ret;
  324. }
  325. static void mtk_drm_unbind(struct device *dev)
  326. {
  327. struct mtk_drm_private *private = dev_get_drvdata(dev);
  328. drm_dev_unregister(private->drm);
  329. drm_dev_put(private->drm);
  330. private->drm = NULL;
  331. }
  332. static const struct component_master_ops mtk_drm_ops = {
  333. .bind = mtk_drm_bind,
  334. .unbind = mtk_drm_unbind,
  335. };
  336. static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
  337. { .compatible = "mediatek,mt2701-disp-ovl",
  338. .data = (void *)MTK_DISP_OVL },
  339. { .compatible = "mediatek,mt8173-disp-ovl",
  340. .data = (void *)MTK_DISP_OVL },
  341. { .compatible = "mediatek,mt2701-disp-rdma",
  342. .data = (void *)MTK_DISP_RDMA },
  343. { .compatible = "mediatek,mt8173-disp-rdma",
  344. .data = (void *)MTK_DISP_RDMA },
  345. { .compatible = "mediatek,mt8173-disp-wdma",
  346. .data = (void *)MTK_DISP_WDMA },
  347. { .compatible = "mediatek,mt2701-disp-color",
  348. .data = (void *)MTK_DISP_COLOR },
  349. { .compatible = "mediatek,mt8173-disp-color",
  350. .data = (void *)MTK_DISP_COLOR },
  351. { .compatible = "mediatek,mt8173-disp-aal",
  352. .data = (void *)MTK_DISP_AAL},
  353. { .compatible = "mediatek,mt8173-disp-gamma",
  354. .data = (void *)MTK_DISP_GAMMA, },
  355. { .compatible = "mediatek,mt8173-disp-ufoe",
  356. .data = (void *)MTK_DISP_UFOE },
  357. { .compatible = "mediatek,mt2701-dsi",
  358. .data = (void *)MTK_DSI },
  359. { .compatible = "mediatek,mt8173-dsi",
  360. .data = (void *)MTK_DSI },
  361. { .compatible = "mediatek,mt2701-dpi",
  362. .data = (void *)MTK_DPI },
  363. { .compatible = "mediatek,mt8173-dpi",
  364. .data = (void *)MTK_DPI },
  365. { .compatible = "mediatek,mt2701-disp-mutex",
  366. .data = (void *)MTK_DISP_MUTEX },
  367. { .compatible = "mediatek,mt2712-disp-mutex",
  368. .data = (void *)MTK_DISP_MUTEX },
  369. { .compatible = "mediatek,mt8173-disp-mutex",
  370. .data = (void *)MTK_DISP_MUTEX },
  371. { .compatible = "mediatek,mt2701-disp-pwm",
  372. .data = (void *)MTK_DISP_BLS },
  373. { .compatible = "mediatek,mt8173-disp-pwm",
  374. .data = (void *)MTK_DISP_PWM },
  375. { .compatible = "mediatek,mt8173-disp-od",
  376. .data = (void *)MTK_DISP_OD },
  377. { }
  378. };
  379. static int mtk_drm_probe(struct platform_device *pdev)
  380. {
  381. struct device *dev = &pdev->dev;
  382. struct mtk_drm_private *private;
  383. struct resource *mem;
  384. struct device_node *node;
  385. struct component_match *match = NULL;
  386. int ret;
  387. int i;
  388. private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
  389. if (!private)
  390. return -ENOMEM;
  391. mutex_init(&private->commit.lock);
  392. INIT_WORK(&private->commit.work, mtk_atomic_work);
  393. private->data = of_device_get_match_data(dev);
  394. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  395. private->config_regs = devm_ioremap_resource(dev, mem);
  396. if (IS_ERR(private->config_regs)) {
  397. ret = PTR_ERR(private->config_regs);
  398. dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
  399. ret);
  400. return ret;
  401. }
  402. /* Iterate over sibling DISP function blocks */
  403. for_each_child_of_node(dev->of_node->parent, node) {
  404. const struct of_device_id *of_id;
  405. enum mtk_ddp_comp_type comp_type;
  406. int comp_id;
  407. of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
  408. if (!of_id)
  409. continue;
  410. if (!of_device_is_available(node)) {
  411. dev_dbg(dev, "Skipping disabled component %pOF\n",
  412. node);
  413. continue;
  414. }
  415. comp_type = (enum mtk_ddp_comp_type)of_id->data;
  416. if (comp_type == MTK_DISP_MUTEX) {
  417. private->mutex_node = of_node_get(node);
  418. continue;
  419. }
  420. comp_id = mtk_ddp_comp_get_id(node, comp_type);
  421. if (comp_id < 0) {
  422. dev_warn(dev, "Skipping unknown component %pOF\n",
  423. node);
  424. continue;
  425. }
  426. private->comp_node[comp_id] = of_node_get(node);
  427. /*
  428. * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have
  429. * separate component platform drivers and initialize their own
  430. * DDP component structure. The others are initialized here.
  431. */
  432. if (comp_type == MTK_DISP_COLOR ||
  433. comp_type == MTK_DISP_OVL ||
  434. comp_type == MTK_DISP_RDMA ||
  435. comp_type == MTK_DSI ||
  436. comp_type == MTK_DPI) {
  437. dev_info(dev, "Adding component match for %pOF\n",
  438. node);
  439. drm_of_component_match_add(dev, &match, compare_of,
  440. node);
  441. } else {
  442. struct mtk_ddp_comp *comp;
  443. comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
  444. if (!comp) {
  445. ret = -ENOMEM;
  446. goto err_node;
  447. }
  448. ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL);
  449. if (ret)
  450. goto err_node;
  451. private->ddp_comp[comp_id] = comp;
  452. }
  453. }
  454. if (!private->mutex_node) {
  455. dev_err(dev, "Failed to find disp-mutex node\n");
  456. ret = -ENODEV;
  457. goto err_node;
  458. }
  459. pm_runtime_enable(dev);
  460. platform_set_drvdata(pdev, private);
  461. ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
  462. if (ret)
  463. goto err_pm;
  464. return 0;
  465. err_pm:
  466. pm_runtime_disable(dev);
  467. err_node:
  468. of_node_put(private->mutex_node);
  469. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  470. of_node_put(private->comp_node[i]);
  471. return ret;
  472. }
  473. static int mtk_drm_remove(struct platform_device *pdev)
  474. {
  475. struct mtk_drm_private *private = platform_get_drvdata(pdev);
  476. struct drm_device *drm = private->drm;
  477. int i;
  478. drm_dev_unregister(drm);
  479. mtk_drm_kms_deinit(drm);
  480. drm_dev_put(drm);
  481. component_master_del(&pdev->dev, &mtk_drm_ops);
  482. pm_runtime_disable(&pdev->dev);
  483. of_node_put(private->mutex_node);
  484. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  485. of_node_put(private->comp_node[i]);
  486. return 0;
  487. }
  488. #ifdef CONFIG_PM_SLEEP
  489. static int mtk_drm_sys_suspend(struct device *dev)
  490. {
  491. struct mtk_drm_private *private = dev_get_drvdata(dev);
  492. struct drm_device *drm = private->drm;
  493. int ret;
  494. ret = drm_mode_config_helper_suspend(drm);
  495. DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n");
  496. return ret;
  497. }
  498. static int mtk_drm_sys_resume(struct device *dev)
  499. {
  500. struct mtk_drm_private *private = dev_get_drvdata(dev);
  501. struct drm_device *drm = private->drm;
  502. int ret;
  503. ret = drm_mode_config_helper_resume(drm);
  504. DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n");
  505. return ret;
  506. }
  507. #endif
  508. static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
  509. mtk_drm_sys_resume);
  510. static const struct of_device_id mtk_drm_of_ids[] = {
  511. { .compatible = "mediatek,mt2701-mmsys",
  512. .data = &mt2701_mmsys_driver_data},
  513. { .compatible = "mediatek,mt2712-mmsys",
  514. .data = &mt2712_mmsys_driver_data},
  515. { .compatible = "mediatek,mt8173-mmsys",
  516. .data = &mt8173_mmsys_driver_data},
  517. { }
  518. };
  519. static struct platform_driver mtk_drm_platform_driver = {
  520. .probe = mtk_drm_probe,
  521. .remove = mtk_drm_remove,
  522. .driver = {
  523. .name = "mediatek-drm",
  524. .of_match_table = mtk_drm_of_ids,
  525. .pm = &mtk_drm_pm_ops,
  526. },
  527. };
  528. static struct platform_driver * const mtk_drm_drivers[] = {
  529. &mtk_ddp_driver,
  530. &mtk_disp_color_driver,
  531. &mtk_disp_ovl_driver,
  532. &mtk_disp_rdma_driver,
  533. &mtk_dpi_driver,
  534. &mtk_drm_platform_driver,
  535. &mtk_dsi_driver,
  536. &mtk_mipi_tx_driver,
  537. };
  538. static int __init mtk_drm_init(void)
  539. {
  540. return platform_register_drivers(mtk_drm_drivers,
  541. ARRAY_SIZE(mtk_drm_drivers));
  542. }
  543. static void __exit mtk_drm_exit(void)
  544. {
  545. platform_unregister_drivers(mtk_drm_drivers,
  546. ARRAY_SIZE(mtk_drm_drivers));
  547. }
  548. module_init(mtk_drm_init);
  549. module_exit(mtk_drm_exit);
  550. MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
  551. MODULE_DESCRIPTION("Mediatek SoC DRM driver");
  552. MODULE_LICENSE("GPL v2");