intel_uncore.h 7.2 KB

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  1. /*
  2. * Copyright © 2017 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. */
  24. #ifndef __INTEL_UNCORE_H__
  25. #define __INTEL_UNCORE_H__
  26. #include <linux/spinlock.h>
  27. #include <linux/notifier.h>
  28. #include <linux/hrtimer.h>
  29. #include "i915_reg.h"
  30. struct drm_i915_private;
  31. enum forcewake_domain_id {
  32. FW_DOMAIN_ID_RENDER = 0,
  33. FW_DOMAIN_ID_BLITTER,
  34. FW_DOMAIN_ID_MEDIA,
  35. FW_DOMAIN_ID_MEDIA_VDBOX0,
  36. FW_DOMAIN_ID_MEDIA_VDBOX1,
  37. FW_DOMAIN_ID_MEDIA_VDBOX2,
  38. FW_DOMAIN_ID_MEDIA_VDBOX3,
  39. FW_DOMAIN_ID_MEDIA_VEBOX0,
  40. FW_DOMAIN_ID_MEDIA_VEBOX1,
  41. FW_DOMAIN_ID_COUNT
  42. };
  43. enum forcewake_domains {
  44. FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
  45. FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),
  46. FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
  47. FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
  48. FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
  49. FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
  50. FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
  51. FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
  52. FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
  53. FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
  54. };
  55. struct intel_uncore_funcs {
  56. void (*force_wake_get)(struct drm_i915_private *dev_priv,
  57. enum forcewake_domains domains);
  58. void (*force_wake_put)(struct drm_i915_private *dev_priv,
  59. enum forcewake_domains domains);
  60. u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
  61. i915_reg_t r, bool trace);
  62. u16 (*mmio_readw)(struct drm_i915_private *dev_priv,
  63. i915_reg_t r, bool trace);
  64. u32 (*mmio_readl)(struct drm_i915_private *dev_priv,
  65. i915_reg_t r, bool trace);
  66. u64 (*mmio_readq)(struct drm_i915_private *dev_priv,
  67. i915_reg_t r, bool trace);
  68. void (*mmio_writeb)(struct drm_i915_private *dev_priv,
  69. i915_reg_t r, u8 val, bool trace);
  70. void (*mmio_writew)(struct drm_i915_private *dev_priv,
  71. i915_reg_t r, u16 val, bool trace);
  72. void (*mmio_writel)(struct drm_i915_private *dev_priv,
  73. i915_reg_t r, u32 val, bool trace);
  74. };
  75. struct intel_forcewake_range {
  76. u32 start;
  77. u32 end;
  78. enum forcewake_domains domains;
  79. };
  80. struct intel_uncore {
  81. spinlock_t lock; /** lock is also taken in irq contexts. */
  82. const struct intel_forcewake_range *fw_domains_table;
  83. unsigned int fw_domains_table_entries;
  84. struct notifier_block pmic_bus_access_nb;
  85. struct intel_uncore_funcs funcs;
  86. unsigned int fifo_count;
  87. enum forcewake_domains fw_domains;
  88. enum forcewake_domains fw_domains_active;
  89. enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
  90. u32 fw_set;
  91. u32 fw_clear;
  92. u32 fw_reset;
  93. struct intel_uncore_forcewake_domain {
  94. enum forcewake_domain_id id;
  95. enum forcewake_domains mask;
  96. unsigned int wake_count;
  97. bool active;
  98. struct hrtimer timer;
  99. i915_reg_t reg_set;
  100. i915_reg_t reg_ack;
  101. } fw_domain[FW_DOMAIN_ID_COUNT];
  102. struct {
  103. unsigned int count;
  104. int saved_mmio_check;
  105. int saved_mmio_debug;
  106. } user_forcewake;
  107. int unclaimed_mmio_check;
  108. };
  109. /* Iterate over initialised fw domains */
  110. #define for_each_fw_domain_masked(domain__, mask__, dev_priv__, tmp__) \
  111. for (tmp__ = (mask__); \
  112. tmp__ ? (domain__ = &(dev_priv__)->uncore.fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
  113. #define for_each_fw_domain(domain__, dev_priv__, tmp__) \
  114. for_each_fw_domain_masked(domain__, (dev_priv__)->uncore.fw_domains, dev_priv__, tmp__)
  115. void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
  116. void intel_uncore_init(struct drm_i915_private *dev_priv);
  117. void intel_uncore_prune(struct drm_i915_private *dev_priv);
  118. bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
  119. bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
  120. void intel_uncore_fini(struct drm_i915_private *dev_priv);
  121. void intel_uncore_suspend(struct drm_i915_private *dev_priv);
  122. void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
  123. void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv);
  124. u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
  125. void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
  126. void assert_forcewakes_active(struct drm_i915_private *dev_priv,
  127. enum forcewake_domains fw_domains);
  128. const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
  129. enum forcewake_domains
  130. intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
  131. i915_reg_t reg, unsigned int op);
  132. #define FW_REG_READ (1)
  133. #define FW_REG_WRITE (2)
  134. void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
  135. enum forcewake_domains domains);
  136. void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
  137. enum forcewake_domains domains);
  138. /* Like above but the caller must manage the uncore.lock itself.
  139. * Must be used with I915_READ_FW and friends.
  140. */
  141. void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
  142. enum forcewake_domains domains);
  143. void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
  144. enum forcewake_domains domains);
  145. void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv);
  146. void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv);
  147. int __intel_wait_for_register(struct drm_i915_private *dev_priv,
  148. i915_reg_t reg,
  149. u32 mask,
  150. u32 value,
  151. unsigned int fast_timeout_us,
  152. unsigned int slow_timeout_ms,
  153. u32 *out_value);
  154. static inline
  155. int intel_wait_for_register(struct drm_i915_private *dev_priv,
  156. i915_reg_t reg,
  157. u32 mask,
  158. u32 value,
  159. unsigned int timeout_ms)
  160. {
  161. return __intel_wait_for_register(dev_priv, reg, mask, value, 2,
  162. timeout_ms, NULL);
  163. }
  164. int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
  165. i915_reg_t reg,
  166. u32 mask,
  167. u32 value,
  168. unsigned int fast_timeout_us,
  169. unsigned int slow_timeout_ms,
  170. u32 *out_value);
  171. static inline
  172. int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
  173. i915_reg_t reg,
  174. u32 mask,
  175. u32 value,
  176. unsigned int timeout_ms)
  177. {
  178. return __intel_wait_for_register_fw(dev_priv, reg, mask, value,
  179. 2, timeout_ms, NULL);
  180. }
  181. #define raw_reg_read(base, reg) \
  182. readl(base + i915_mmio_reg_offset(reg))
  183. #define raw_reg_write(base, reg, value) \
  184. writel(value, base + i915_mmio_reg_offset(reg))
  185. #endif /* !__INTEL_UNCORE_H__ */